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IN74HCT373A Datasheet(PDF) 4 Page - Integral Corp.

Part No. IN74HCT373A
Description  Octal 3-State Noninverting Transparent Latch High-Performance Silicon-Gate CMOS
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Maker  INTEGRAL [Integral Corp.]
Homepage  http://www.iksemi.com/
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IN74HCT373A Datasheet(HTML) 4 Page - Integral Corp.

   
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IN74HCT373A
374
AC ELECTRICAL CHARACTERISTICS(V
CC =5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns)
Guaranteed Limit
Symbol
Parameter
25
°C
to
-55
°C
≤85°C
≤125°C
Unit
tPLH, tPHL
Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
28
35
42
ns
tPLH, tPHL
Maximum Propagation Delay , Latch Enable to Q
(Figures 2 and 5)
32
40
48
ns
tPLZ, tPHZ
Maximum Propagation Delay ,Output Enable to Q
(Figures 3 and 6)
30
38
45
ns
tPZL, tPZH
Maximum Propagation Delay , Output Enable to
Q (Figures 3 and 6)
35
44
53
ns
tTLH, tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
12
15
18
ns
CIN
Maximum Input Capacitance
10
10
10
pF
COUT
Maximum Three-State Output Capacitance
(Output in High-Impedance State)
15
15
15
pF
Power Dissipation Capacitance (Per Latch)
Typical @25
°C,V
CC=5.0 V
CPD
Used to determine the no-load dynamic power
consumption:
PD=CPDVCC
2f+I
CCVCC
65
pF
TIMING REQUIREMENTS (V
CC =5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns)
Guaranteed Limit
Symbol
Parameter
25
°C to
-55
°C
≤85°C
≤125°C
Unit
tSU
Minimum Setup Time, Input D
to Latch Enable
(Figure 4)
10
13
15
ns
th
Minimum Hold Time,Latch
Enable to Input D
(Figure 4)
10
13
15
ns
tw
Minimum Pulse Width, Latch
Enable (Figure 2)
12
15
18
ns
tr, tf
Maximum Input Rise and Fall
Times (Figure 1)
500
500
500
ns


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