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MC9S08PT16 Datasheet(PDF) 30 Page - NXP Semiconductors |
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MC9S08PT16 Datasheet(HTML) 30 Page - NXP Semiconductors |
30 / 37 page Table 18. SPI slave mode timing (continued) Nu m. Symbol Description Min. Max. Unit Comment 4 tLag Enable lag time 1 — tBus — 5 tWSPSCK Clock (SPSCK) high or low time tBus - 30 — ns — 6 tSU Data setup time (inputs) 15 — ns — 7 tHI Data hold time (inputs) 25 — ns — 8 ta Slave access time — tBus ns Time to data active from high-impedance state 9 tdis Slave MISO disable time — tBus ns Hold time to high- impedance state 10 tv Data valid (after SPSCK edge) — 25 ns — 11 tHO Data hold time (outputs) 0 — ns — 12 tRI Rise time input — tBus - 25 ns — tFI Fall time input 13 tRO Rise time output — 25 ns — tFO Fall time output 2 10 6 7 MSB IN BIT 6 . . . 1 SLAVE MSB SLAVE LSB OUT 11 5 5 3 8 4 13 NOTE: Not defined 12 12 11 SEE NOTE 13 9 see note (INPUT) (CPOL=0) SPSCK SPSCK (CPOL=1) SS (INPUT) (INPUT) MOSI (INPUT) MISO (OUTPUT) LSB IN BIT 6 . . . 1 Figure 20. SPI slave mode timing (CPHA = 0) Peripheral operating requirements and behaviors MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020 30 NXP Semiconductors |
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