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MC9S08PT16 Datasheet(PDF) 18 Page - NXP Semiconductors

Part No. MC9S08PT16
Description  8-Bit S08 central processor unit (CPU)
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MC9S08PT16 Datasheet(HTML) 18 Page - NXP Semiconductors

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Table 7. Control timing (continued)
Num
C
Rating
Symbol
Min
Typical1
Max
Unit
5
D
BKGD/MS setup time after issuing background
debug force reset to enter user or BDM modes
tMSSU
500
ns
6
D
BKGD/MS hold time after issuing background
debug force reset to enter user or BDM modes3
tMSH
100
ns
7
D
IRQ pulse width
Asynchronous
path2
tILIH
100
ns
D
Synchronous path4
tIHIL
1.5 × tcyc
ns
8
D
Keyboard interrupt pulse
width
Asynchronous
path2
tILIH
100
ns
D
Synchronous path
tIHIL
1.5 × tcyc
ns
9
C
Port rise and fall time -
standard drive strength
(load = 50 pF)5
tRise
10.2
ns
C
tFall
9.5
ns
C
Port rise and fall time -
high drive strength (load =
50 pF)5
tRise
5.4
ns
C
tFall
4.6
ns
1. Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.
2. This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
3. To enter BDM mode following a POR, BKGD/MS must be held low during the powerup and for a hold time of tMSH after
VDD rises above VLVD.
4. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
5. Timing is shown with respect to 20% VDD and 80% VDD levels, across operating temperature range.
textrst
RESET PIN
Figure 10. Reset timing
tIHIL
KBIPx
tILIH
IRQ/KBIPx
Figure 11. IRQ/KBIPx timing
6.2.2 Debug trace timing specifications
Table 8. Debug trace operating behaviors
Symbol
Description
Min.
Max.
Unit
tcyc
Clock period
Frequency dependent
MHz
Table continues on the next page...
Switching specifications
MC9S08PT16 Series Data Sheet, Rev. 4, 03/2020
18
NXP Semiconductors


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