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AM29LV800D Datasheet(PDF) 20 Page - Advanced Micro Devices

Part # AM29LV800D
Description  8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM29LV800D Datasheet(HTML) 20 Page - Advanced Micro Devices

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Am29LV800D
Am29LV800D_00_A4_E January 21, 2005
PR EL IM IN A R Y
If DQ5 goes high during a program or erase
operation, writing the reset command returns
the device to reading array data (also applies
during Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the
host system to access the manufacturer and
devices codes, and determine whether or not a
sector is protected. Table 5 shows the address
and data requirements. This method is an alter-
native to that shown in Table 4, which is
intended for PROM programmers and requires
VID on address bit A9.
The autoselect command sequence is initiated
by writing two unlock cycles, followed by the
autoselect command. The device then enters
the autoselect mode, and the system may read
at any address any number of times, without
initiating another command sequence.
A read cycle at address XX00h retrieves the
manufacturer code. A read cycle at address
XX01h in word mode (or 02h in byte mode)
returns the device code. A read cycle containing
a sector address (SA) and the address 02h in
word mode (or 04h in byte mode) returns 01h if
that sector is protected, or 00h if it is unpro-
tected. Refer to Tables 2 and 3 for valid sector
addresses.
The system must write the reset command to
exit the autoselect mode and return to reading
array data.
Word/Byte Program Command Sequence
The system may program the device by word or
byte, depending on the state of the BYTE# pin.
Programming is a four-bus-cycle operation. The
program command sequence is initiated by
writing two unlock write cycles, followed by the
program set-up command. The program
address and data are written next, which in turn
initiate the Embedded Program algorithm. The
system is not required to provide further con-
trols or timings. The device automatically pro-
vides internally generated program pulses and
verifies the programmed cell margin. Table 5
shows the address and data requirements for
the byte program command sequence.
When the Embedded Program algorithm is com-
plete, the device then returns to reading array
data and addresses are no longer latched. The
system can determine the status of the program
operation by using DQ7, DQ6, or RY/BY#. See
“Write Operation Status” for information on
these status bits.
Any commands written to the device during the
Embedded Program Algorithm are ignored. Note
that a hardware reset immediately terminates
the programming operation. The program
command sequence should be reinitiated once
the device has reset to reading array data, to
ensure data integrity.
Programming is allowed in any sequence and
across sector boundaries. A bit cannot be pro-
grammed from a “0” back to a “1”.
Attempting to do so may halt the operation and
set DQ5 to “1”, or cause the Data# Polling algo-
rithm to indicate the operation was successful.
However, a succeeding read will show that the
data is still “0”. Only erase operations can
convert a “0” to a “1”.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to
program bytes or words to the device faster
than using the standard program command
sequence. The unlock bypass command
sequence is initiated by first writing two unlock
cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h.
The device then enters the unlock bypass mode.
A two-cycle unlock bypass program command
sequence is all that is required to program in
this mode. The first cycle in this sequence con-
tains the unlock bypass program command,
A0h; the second cycle contains the program
address and data. Additional data is pro-
grammed in the same manner. This mode dis-
penses with the initial two unlock cycles
required in the standard program command
sequence, resulting in faster total programming
time. Table 5 shows the requirements for the
command sequence.
During the unlock bypass mode, only the Unlock
Bypass Program and Unlock Bypass Reset com-
mands are valid. To exit the unlock bypass
mode, the system must issue the two-cycle
unlock bypass reset command sequence. The
first cycle must contain the data 90h; the
second cycle the data 00h. Addresses are don’t
care for both cycles. The device then returns to
reading array data.
Figure 1 illustrates the algorithm for the
program operation. See the Erase/Program
Operations table in “AC Characteristics” for
parameters, and to Figure 1 for timing dia-
grams.


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