2. When ICS is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25

kHz to 39.0625 kHz.

3. See crystal or resonator manufacturer's recommendation.

0.

5. This parameter is characterized and not tested on each device.

6. Proper PC board layout procedures must be followed to achieve specifications.

7. This specification applies to any time the FLL reference source or reference divider is changed, trim value changed, or

changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as

the reference, this specification assumes it is already running.

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise

for a given interval.

XOSC

EXTAL

XTAL

Crystal or Resonator

Figure 14. Typical crystal or resonator circuit

7.2 NVM specifications

This section provides details about program/erase times and program/erase endurance for

the flash memories.

Table 12. Flash clock timing characteristics

C

Characteristic

Symbol

Min

Typical

Max

Unit1

D

NVM Bus frequency

1

—

20

MHz

D

NVM Operating frequency

0.8

1.0

1.05

MHz

C

FLASH Program/erase endurance

across operating temperature

10 k

100 k

—

Cycles

C

Data retention at an average junction

10,000 program/erase cycles

15

100

—

years

Peripheral operating requirements and behaviors

MC9S08PB16 Data Sheet, Rev. 2.1, 11/2019

22

NXP Semiconductors