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FPD750DFN Datasheet(PDF) 3 Page - Filtronic Compound Semiconductors

Part No. FPD750DFN
Description  LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT
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Maker  FILTRONIC [Filtronic Compound Semiconductors]
Homepage  http://www.filtronic.co.uk/
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FPD750DFN Datasheet(HTML) 3 Page - Filtronic Compound Semiconductors

   
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FPD750DFN
LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT
BIASING GUIDELINES
Active bias circuits provide good performance stabilization over variations of operating
temperature, but require a larger number of components compared to self-bias or dual-biased.
Such circuits should include provisions to ensure that Gate bias is applied before Drain bias,
otherwise the pHEMT may be induced to self-oscillate. Contact your Sales Representative for
additional information.
Dual-bias circuits are relatively simple to implement, but will require a regulated negative
voltage supply for depletion-mode devices such as the FPD750DFN.
For standard Class A operation, a 50% of IDSS bias point is recommended. A small amount of
RF gain expansion prior to the onset of compression is normal for this operating point. Note that
pHEMTs, since they are “quasi- E/D mode” devices, exhibit Class AB traits when operated at
50% of IDSS. To achieve a larger separation between P1dB and IP3, an operating point in the 25%
to 33% of IDSS range is suggested.
Such Class AB operation will not degrade the IP3
performance.
PACKAGE OUTLINE (dimensions in mm)
All information and specifications subject to change without notice.
Phone: +1 408 850-5790
http://www.filtronic.co.uk/semis
Revised: 11/14/05
Fax: +1 408 850-5766
Email: sales@filcsi.com


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