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TLE75620-EST Datasheet(PDF) 34 Page - Infineon Technologies AG

Part # TLE75620-EST
Description  SPIDER 12V SPI Driver for Enhanced Relay Control
Download  81 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

TLE75620-EST Datasheet(HTML) 34 Page - Infineon Technologies AG

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Datasheet
34
Rev. 1.0
2017-11-23
TLE75620-EST
SPIDER+ 12V
Power Stages
7
Power Stages
The TLE75620-EST is an eight channels configurable and high-side relay switch. The power stages are built by
N-channel lateral power MOSFET transistors.
There are six auto-configurable channels which can be used either as low-side or as high-side switches. They
adjust the diagnostic and protective functions according their potential at drain and source automatically. For
these channels a charge pump is connected to the output MOSFET gate.
In high-side configuration, the load is connected between ground and source of the power transistor (pins
OUTn_S, n = 2...7). The drains of the power transistors (OUTn_D, with “n” equal to the configurable channel
number) can be connected to any potential between ground and VS. When the drain is connected to VS, the
channel behave like an high-side switch.
In low-side configuration, the source of the power transistors must be connected to GND pin potential (either
directly or through a reverse current blocking diode).
The configuration can be chosen for each of these channels individually, therefore it is feasible to connect one
or more channels in low-side configuration, while the remaining auto-configurable are used as high-side
switches.
7.1
Output ON-state resistance
The ON-state resistance RDS(ON) depends on the supply voltage as well as the junction temperature TJ.
7.1.1
Switching Resistive Loads
When switching resistive loads the following switching times and slew rates can be considered.
Figure 16 Switching a Resistive Load
7.1.2
Inductive Output Clamp
When switching off inductive loads, the voltage across the power switch rises to VDS(CL) potential, because the
inductance intends to continue driving the current. The potential at Output pin is not allowed to go below
VOUT_S(CL) or VOUT(CL). The voltage clamping is necessary to prevent device destruction.
VDS
t
SwitchON .emf
tON
tOFF
t
90% of VS
dV /
dtON
70%
dV /
dtOFF
30%
tDELAY(ON)
tDELAY(OFF)
INn /
OUT.OUTn
70% of VS
30% of VS
10% of VS


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