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TS823 Datasheet(PDF) 3 Page - Taiwan Semiconductor Company, Ltd

Part No. TS823
Description  Microprocessor Supervisory Circuit with Watchdog Timer & Manual Reset
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Maker  TSC [Taiwan Semiconductor Company, Ltd]
Homepage  http://www.taiwansemi.com
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TS823 Datasheet(HTML) 3 Page - Taiwan Semiconductor Company, Ltd

   
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TS823/824/825
3-6
2003/12 rev. A
Detail Description
Pin Function
** RESET
RESET is active low.
** GND
Ground
** (RESET)
(RESET) is active high.
** MR
This pin is active low. Pulling this pin low to forces a
reset. After a low to high transition reset remains
asserted for exactly one reset timeout period. This pin
is internally pulled high. If this function is unused then
float this pin or tie it to Vdd.
** WDI
Watch Dog Input. Any transition on this pin will reset
the Watch Dog timer. If this pin remains high or low for
longer than the Watch Dog interval then a reset is
asserted. Float or tri-state this pin to disable the Watch
Dog feature.
** Vdd
Positive power supply. A reset is asserted after this
voltage drops below a predetermined level. After Vdd
rises above that level reset remains asserted until the
end of the reset timeout period.
Applications Information
The TS823/824/825 are designed to interface with the
reset input of a microprocessor and to prevent CPU
execution errors due to power up, power down, and
other power supply errors. The TS823/824 also monitor
the CPU health by checking for signal transitions form
the CPU at the WDI input.
Reset Output
Active low reset outputs are denoted as RESET, Active
high reset output are denoted as (RESET),
A reset will be asserted if any of three things happen:
1)
Vdd drops below the threshold (Vth)
2)
The MR pin is pulled low.
3)
The WDI pin does not detect a transition within the
Watch Dog interval (TWD)
The reset will remain asserted for the prescribed reset
interval after:
1)
Vdd rises above the threshold (Vth)
2)
MR goes high
3)
The Watch Dog timer have timed out causing the
reset to assert.
Manual Reset Input
The TS823 and TS825 feature a manual reset feature
(MR). A logic low on the MR pin asserts a reset. The
reset remains asserted a long as the MR pin remains
low. After the MR pin transitions to a high state the reset
remains asserted for the prescribed reset interval (TD2).
The MR pin is internally pulled up to Vdd by a 100KΩ
resistor. It is internally de-bounced to reject switching
transients.
The MR pin is ESD protected by diodes connected to
Vdd and Gnd. So the MR pin should never be driven
higher than Vdd or lower than Gnd.
Watchdog Input
The TS823 and TS824 are equipped with a watchdog
input (WDI). If the microprocessor does not produce a
valid logic edge at the watchdog input (WDI) within the
prescribed watchdog interval (TWD) then a reset asserts.
The reset remains asserted for the required reset
interval (TD2). Ata the end of the reset interval the reset
is deasserted and the watchdog interval timer starts
again from zero.
If the watchdog input is left unconnected or is connected
to a tri-stated buffer the watchdog function is disabled.
As soon as the WDI input is driven either low or high the
watchdog function resumes with the watchdog timer set
to zero.


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