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MC10H181 Datasheet(PDF) 4 Page - ON Semiconductor

Part No. MC10H181
Description  4-BIT ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC10H181 Datasheet(HTML) 4 Page - ON Semiconductor

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MC10H181
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ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5.0%) (See Note 1.)
0
°
+25
°
+75
°
Characteristic
Symbol
Min
Max
Min
Max
Min
Max
Unit
Power Supply Current
IE
159
145
159
mA
Input Current High
Pin 22
Pins 14,23
Pins 13,15,17
Pins 10,16,18,21
Pins 9,11,19,20
IinH
720
405
515
475
465
450
255
320
300
275
450
255
320
300
275
µA
Input Current Low
Pins 9–11, 13–22
IinL
0.5
0.5
0.3
µA
High Output Voltage
VOH
–1.02
–0.84
–0.98
–0.81
–0.92
–0.735
Vdc
Low Output Voltage
VOL
–1.95
–1.63
–1.95
–1.63
–1.95
–1.60
Vdc
High Input Voltage
VIH
–1.17
–0.84
–1.13
–0.81
–1.07
–0.735
Vdc
Low Input Voltage
VIL
–1.95
–1.48
–1.95
–1.48
–1.95
–1.45
Vdc
1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained.
Outputs are terminated through a 50–ohm resistor to –2.0 volts.
AC PARAMETERS
AC Switching Characteristics
0
°C
+25
°C
+75
°C
Characteristic
Symbol
Input
Output
Conditions
Min
Max
Min
Max
Min
Max
Unit
Propagation Delay
Rise Time, Fall Time
t+ +, t– –
t+, t–
Cn
Cn
Cn+4
Cn+4
A0,A1,A2,A3
A0,A1,A2,A3
0.7
0.6
2.0
2.0
0.7
0.6
2.0
2.0
0.7
0.7
2.2
2.2
ns
ns
Propagation Delay
Rise Time, Fall Time
t+ +, t+ –,
t– +, t– –
t+, t–
Cn
Cn
Cn
F1
F1
F1
A0
1.0
0.7
3.0
2.2
1.0
0.7
3.0
2.2
1.2
0.7
3.3
2.4
ns
Propagation Delay
Rise Time, Fall Time
t+ +, t+ –,
t– +, t– –
t+, t–
A1
A1
A1
F1
F1
F1
1.5
0.7
3.7
2.0
1.5
0.7
3.7
2.0
1.6
0.7
4.0
2.2
ns
Propagation Delay
Rise Time, Fall Time
t+ +, t– –
t+, t–
A1
A1
PG
PG
S0,S3
S0,S3
1.5
0.9
3.7
2.4
1.5
0.9
3.7
2.4
1.6
0.9
4.0
2.6
ns
ns
Propagation Delay
Rise Time, Fall Time
t+ +, t– –
t+, t–
A1
A1
GG
GG
A0,A2,A3,Cn
A0,A2,A3,Cn
1.5
0.7
3.7
2.2
1.5
0.7
3.7
2.2
1.6
0.7
3.9
2.4
ns
ns
Propagation Delay
Rise Time, Fall Time
t+ –, t– +
t+, t–
A1
A1
Cn+4
Cn+4
A0,A2,A3,Cn
A0,A2,A3,Cn
1.5
0.5
3.6
2.0
1.5
0.5
3.6
2.0
1.6
0.5
3.9
2.2
ns
ns
Propagation Delay
Rise Time, Fall Time
t+ +, t– +
t+, t–
B1
B1
F1
F
S3,Cn
S3,Cn
2.0
0.7
4.5
2.3
2.0
0.7
4.5
2.3
2.1
0.7
4.8
2.5
ns
ns
Propagation Delay
Rise Time, Fall Time
t+ +, t– –
t+, t–
B1
B1
PG
PG
S0,A1
S0,A1
1.5
0.7
3.8
2.2
1.5
0.7
3.8
2.2
1.6
0.7
4.0
2.4
ns
ns
Propagation Delay
Rise Time, Fall Time
t+ +, t– –
t+, t–
B1
B1
GG
GG
S3,Cn
S3,Cn
1.5
0.7
3.7
2.2
1.5
0.7
3.7
2.2
1.6
0.7
4.0
2.4
ns
ns
Propagation Delay
Rise Time, Fall Time
t+ –, t– +
t+, t–
B1
B1
Cn+4
Cn+4
S3,Cn
S3,Cn
2.0
0.5
4.0
2.0
2.0
0.5
4.0
2.2
2.1
0.5
4.3
2.2
ns
ns
Propagation Delay
Rise Time, Fall Time
t+ +, t+ –
t+, t–
M
M
F1
F1
1.5
0.8
4.2
2.3
1.5
0.8
4.2
2.3
1.6
0.8
4.5
2.5
ns
ns
Propagation Delay
Rise Time, Fall Time
t+ –, t– +
t+, t–
S1
S1
F1
F1
A1,B1
A1,B1
1.5
0.7
4.5
2.0
1.5
0.7
4.5
2.0
1.6
0.7
4.8
2.2
ns
ns
Propagation Delay
Rise Time, Fall Time
t– +, t+ –
t+, t–
S1
S1
PG
PG
A3,B3
A3,B3
1.5
0.7
4.0
2.0
1.5
0.7
4.0
2.2
1.6
0.7
4.3
2.4
ns
ns
Propagation Delay
Rise Time, Fall Time
t+ –, t– +
t+, t–
S1
S1
Cn+4
Cn+4
A3,B3
A3,B3
1.5
0.7
4.1
2.2
1.5
0.7
4.1
2.2
1.6
0.7
4.4
2.4
ns
ns
Propagation Delay
Rise Time, Fall Time
t+ –, t– +
t+, t–
S1
S1
GG
GG
A3,B3
A3,B3
1.3
0.5
4.5
3.2
1.3
0.5
4.5
3.2
1.4
0.5
4.8
3.4
ns
ns
† Logic high level (+1.11 Vdc) applied to pins listed. All other input pins are left floating or tied to +0.31 Vdc.
VCC1 = VCC2 = +2.0 Vdc, VEE = –3.2 Vdc


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