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MC84-74HC393 Datasheet(PDF) 3 Page - ON Semiconductor

Part No. MC84-74HC393
Description  Dual 4-Stage Binary Ripple Counter
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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MC84-74HC393 Datasheet(HTML) 3 Page - ON Semiconductor

   
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MC54/74HC393
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
VCC
V
Guaranteed Limit
Unit
Symbol
Parameter
VCC
V
– 55 to
25
_C
v 85_C
v 125_C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 3)
2.0
4.5
6.0
5.4
27
32
4.4
22
26
3.6
18
21
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock to Q1
(Figures 1 and 3)
2.0
4.5
6.0
120
24
20
150
30
26
180
36
31
ns
tPLH,
tPHL
Maximum Propagation Delay, Clock to Q2
(Figures 1 and 3)
2.0
4.5
6.0
190
38
32
240
48
41
285
57
48
ns
tPLH,
tPHL
Maximum Propagation Delay, Clock to Q3
(Figures 1 and 3)
2.0
4.5
6.0
240
48
41
300
60
51
360
72
61
ns
tPLH,
tPHL
Maximum Propagation Delay, Clock to Q4
(Figures 1 and 3)
2.0
4.5
6.0
290
58
49
365
73
62
435
87
74
ns
tPHL
Maximum Propagation Delay, Reset to any Q
(Figures 2 and 3)
2.0
4.5
6.0
165
33
28
205
41
35
250
50
43
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Cin
Maximum Input Capacitance
10
10
10
pF
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
CPD
Power Dissipation Capacitance (Per Counter)*
Typical @ 25
°C, VCC = 5.0 V
pF
CPD
Power Dissipation Capacitance (Per Counter)*
40
pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Symbol
Parameter
VCC
V
Guaranteed Limit
Unit
Symbol
Parameter
VCC
V
– 55 to
25
_C
v 85_C
v 125_C
Unit
trec
Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
ns
tw
Minimum Pulse Width, Clock
(Figure 1)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tw
Minimum Pulse Width, Reset
(Figure 2)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).


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