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M45PE40-VMP6G Datasheet(PDF) 16 Page - STMicroelectronics |
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M45PE40-VMP6G Datasheet(HTML) 16 Page - STMicroelectronics |
16 / 35 page M45PE40 16/35 Read Data Bytes at Higher Speed (FAST_READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 12.. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shift- ed out. The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ) instruction. When the highest ad- dress is reached, the address counter rolls over to 000000h, allowing the read sequence to be contin- ued indefinitely. The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving Chip Select (S) High. Chip Select (S) can be driv- en High at any time during data output. Any Read Data Bytes at Higher Speed (FAST_READ) in- struction, while an Erase, Program or Write cycle is in progress, is rejected without having any ef- fects on the cycle that is in progress. Figure 12. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out Sequence Note: Address bits A23 to A19 are Don’t Care. C D AI04006 S Q 23 2 1 3456789 10 28 29 30 31 22 21 3210 High Impedance Instruction 24 BIT ADDRESS 0 C D S Q 32 33 34 36 37 38 39 40 41 42 43 44 45 46 765432 0 1 DATA OUT 1 Dummy Byte MSB 7 6543210 DATA OUT 2 MSB MSB 7 47 765432 0 1 35 |
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