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M45PE40 Datasheet(PDF) 8 Page - STMicroelectronics

Part No. M45PE40
Description  4 Mbit, Low Voltage, Page-Erasable Serial Flash Memory With Byte-Alterability and a 33 MHz SPI Bus Interface
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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M45PE40 Datasheet(HTML) 8 Page - STMicroelectronics

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mode until another specific instruction (the Re-
lease from Deep Power-down and Read Electron-
ic Signature (RES) instruction) is executed.
All other instructions are ignored while the device
is in the Deep Power-down mode. This can be
used as an extra software protection mechanism,
when the device is not in active use, to protect the
device from inadvertent Write, Program or Erase
instructions.
Status Register
The Status Register contains two status bits that
can be read by the Read Status Register (RDSR)
instruction.
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write, Program
or Erase cycle.
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
Table 2. Status Register Format
Note: WEL and WIP are volatile read-only bits (WEL is set and re-
set by specific instructions; WIP is automatically set and re-
set by the internal logic of the device).
Protection Modes
The environments where non-volatile memory de-
vices are used can be very noisy. No SPI device
can operate correctly in the presence of excessive
noise. To help combat this, the M45PE40 features
the following data protection mechanisms:
Power On Reset and an internal timer (tPUW)
can provide protection against inadvertant
changes while the power supply is outside the
operating specification.
Program, Erase and Write instructions are
checked that they consist of a number of clock
pulses that is a multiple of eight, before they
are accepted for execution.
All instructions that modify data must be
preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch
(WEL) bit. This bit is returned to its reset state
by the following events:
Power-up
Reset (RESET) driven Low
Write Disable (WRDI) instruction
completion
Page Write (PW) instruction completion
Page Program (PP) instruction completion
Page Erase (PE) instruction completion
Sector Erase (SE) instruction completion
The Hardware Protected mode is entered
when Write Protect (W) is driven Low, causing
the first 256 pages of memory to become
read-only. When Write Protect (W) is driven
High, the first 256 pages of memory behave
like the other pages of memory
The Reset (Reset) signal can be driven Low to
protect the contents of the memory during any
critical time, not just during Power-up and
Power-down.
In addition to the low power consumption
feature, the Deep Power-down mode offers
extra software protection from inadvertant
Write, Program and Erase instructions while
the device is not in active use.
b7
b0
0
0
0
0
0
0
WEL
WIP


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