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MC74VHCT125A Datasheet(PDF) 1 Page - ON Semiconductor

Part No. MC74VHCT125A
Description  Quad Bus Buffer
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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MC74VHCT125A Datasheet(HTML) 1 Page - ON Semiconductor

   
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© Semiconductor Components Industries, LLC, 2000
April, 2000 – Rev. 1
1
Publication Order Number:
MC74VHCT125A/D
MC74VHCT125A
Quad Bus Buffer
with 3–State Control Inputs
The MC74VHCT125A is a high speed CMOS quad bus buffer
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The MC74VHCT125A requires the 3–state control input (OE) to be
set High to place the output into the high impedance state.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3V to 5.0V, because it has
full 5V CMOS level output swings.
The VHCT125A input structures provide protection when voltages
between 0V and 5.5V are applied, regardless of the supply voltage.
The output structures also provide protection when VCC = 0V. These
input and output structures help prevent device destruction caused by
supply voltage – input/output voltage mismatch, battery backup, hot
insertion, etc.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7V, allowing the interface of 5V systems
to 3V systems.
High Speed: tPD = 3.8ns (Typ) at VCC = 5V
Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C
TTL–Compatible Inputs: VIL = 0.8V; VIH = 2.0V
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2V to 5.5V Operating Range
Low Noise: VOLP = 0.8V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance: HBM > 2000V; Machine Model > 200V
Chip Complexity: 72 FETs or 18 Equivalent Gates
LOGIC DIAGRAM
Active–Low Output Enables
Y1
Y2
Y4
3
6
8
11
13
12
10
9
4
5
1
2
A1
OE1
A2
OE2
A3
OE3
A4
OE4
Y3
FUNCTION TABLE
VHCT125A
Inputs
Output
AOE
Y
HL
H
LL
L
XH
Z
14–LEAD SOIC
D SUFFIX
CASE 751A
http://onsemi.com
14–LEAD TSSOP
DT SUFFIX
CASE 948G
PIN CONNECTION AND
MARKING DIAGRAM (Top View)
Device
Package
Shipping
ORDERING INFORMATION
MC74VHCT125AD
SOIC
55 Units/Rail
MC74VHCT125ADT
TSSOP
96 Units/Rail
14–LEAD SOIC EIAJ
M SUFFIX
CASE 965
MC74VHCT125AM
SOIC EIAJ
50 Units/Rail
For detailed package marking information, see the Marking
Diagram section on page 4 of this data sheet.
11
12
13
14
8
9
10
5
4
3
2
1
7
6
OE3
Y4
A4
OE4
VCC
Y3
A3
OE2
Y1
A1
OE1
GND
Y2
A2


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