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TMAG5170-Q1 Datasheet(PDF) 19 Page - Texas Instruments |
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TMAG5170-Q1 Datasheet(HTML) 19 Page - Texas Instruments |
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19 / 45 page  MOSI: Read or Write Read or write command Seven bit address to access registers Sixteen bit data to be written, don[t care during read command Command bits to instruct read type and start new conversion CRC bits CMD0 = 0 No conversion start through command bits CMD0 = 1 Start of conversion at the CS going high CMD1 = 0 Display SET_COUNT [2:0] in STAT [2:0] bits at MISO next frame CMD1 = 1 Display DATA_TYPE [2:0] in STAT [2:0] bits at MISO next frame CMD0 CMD1 * CMD2 & CMD3 are reserved bits ** SET_COUNT register bits indicate the rolling count of the conversion data set . The counter is reset after 111b. *** DATA_TYPE register bits indicate the type of data being read through the MISO line 19 TMAG5170-Q1 www.ti.com SBAS934 – JUNE 2020 Product Folder Links: TMAG5170-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Programming (continued) Figure 10. 32-Bit Frame Definition of the MOSI Line 7.5.2.4 MISO The 'master in, slave out' (MISO) line is used by the master to read the data from the TMAG5170-Q1. The TMAG5170-Q1 will shift out command responses and ADC conversion data serially with each rising SCLK edge when the CS pin is low. This pin assumes a high-impedance state when CS is high. Based off the DATA_TYPE bit setting, the TMAG5170-Q1 supports two different MISO frames: • Regular 32-Bit MISO Read • Special 32-Bit MISO Read 7.5.2.4.1 Regular 32-Bit MISO Read With DATA_TYPE = 000b, the TMAG5170-Q1 supports a regular 16-bit register read during the 32-bit MISO frame as explained in Figure 11. In this read mode, 12-bit status bits are displayed. All the status bits except for the ERROR_STAT bit are directly read from the status registers. The ERROR_STAT bit indicates if any error bit set in the device. The status bits STAT[2:0] can be changed based off CMD1 value in the previous frame as described in Figure 11. |
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