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ICL7112JCDL Datasheet(PDF) 4 Page - Intersil Corporation

Part # ICL7112JCDL
Description  12-Bit, High-Speed, CMOS uP-Compatible A/D Converter
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ICL7112JCDL Datasheet(HTML) 4 Page - Intersil Corporation

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6-4
High State
Input Voltage
VIH
TMIN -TMAX
2.4
-
-
2.4
-
-
2.4
-
-
V
Logic Input
Current
ILIH
0 < VIN < V+
-
1
10
-1
10
-1
10
µA
Logic Input
Capacitance
CIN
-
15
-
-15
-
-15
-
pF
LOGIC OUTPUT
Low State Output
Voltage
VOL
IOUT = 1.6mA
TMIN -TMAX
--
0.4
-
-
0.4
-
-
0.4
V
High State Output
Voltage
VOH
IOUT = -200µA
TMIN -TMAX
2.8
-
-
2.8
-
-
2.8
-
-
V
Three-State Output
Current
IOX
0 < VOUT < V+
-1
-
-
1
-
-
1
-
µA
Logic Output
Capacitance
COUT
Three-State
-
15
-
-
15
-
-
15
-
pF
POWER REQUIREMENTS
Supply Voltage
Range
VSUPPLY Functional Operation Only ±4.5
-
±6.0
±4.5
-
±6.0
±4.5
-
±6.0
V
Supply Current,
I+, I-
ISUPPLY
RM
TMIN -TMAX
-2
4
6
-2
4
6
-2
4
6
mA
NOTES:
4. Full scale range (FSR) is 10V (reference adjusted).
5. Assume all leads are soldered or welded to printed circuit board.
6. “J” and “K” versions not production tested. Guaranteed by Integral Linearity Test.
7. Typical values are not tested, for reference only.
8. Not production tested. Guaranteed by design.
Electrical Specifications Test Conditions: V+ = +5V, V- = -5V, VREF = -10V, TA = 25oC, fCLK = 500kHz, Unless Otherwise Noted
PARAMETER
SYMBOL
TEST
CONDITIONS
JK
L
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
AC Electrical Specifications Test Conditions V+ = +5V, V- = -5V, TA = 25oC, fCLK = 500kHz, unless otherwise noted. Data
derived from extensive characterization testing. Parameters are not production tested
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNITS
READ CYCLE TIMING
Propagation Delay CS to Date
tcd
RD Low, A0 Valid
-
-
200
ns
Propagation Delay A0 to Data
tad
CS Low, RD Low
-
-
200
Propagation Delay RD to Data
trd
CS Low, A0 Valid
-
-
200
Propagation Delay Data to Three-State
trx
--
150
Propagation Delay EOC High to Data
ted
--
200
WRITE CYCLE TIMING
WR Low Time
twr
150
-
-
ns
Propagation Delay WR Low to EOC Low
twe
Wait Mode
1
-
2
EOC High Time
teo
Free Run Mode
0.5
-
1.5
1/fCLK
Conversion Time
tconv
--
20
Clock Frequency Range
fCLK
Functional Operation Only
-
500
-
kHz
NOTE:
9. All typical values have been characterized, but are not tested.
ICL7112


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