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HI5667 Datasheet(PDF) 5 Page - Intersil Corporation

Part No. HI5667
Description  8-Bit, 60MSPS A/D Converter with Internal Voltage Reference
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

HI5667 Datasheet(HTML) 5 Page - Intersil Corporation

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5
Reference Temperature Coefficient
-
120
-
ppm/oC
REFERENCE VOLTAGE INPUT
Reference Voltage Input, VREFIN
-2.5
-
V
Total Reference Resistance, RREFIN
-2.5
-
k
Reference Input Current, IREFIN
-1
-
mA
DC BIAS VOLTAGE
DC Bias Voltage Output, VDC
-3.0
-
V
Maximum Output Current
--
0.2
mA
DIGITAL INPUTS
Input Logic High Voltage, VIH
CLK, DFS, OE
2.0
-
-
V
Input Logic Low Voltage, VIL
CLK, DFS, OE
--
0.8
V
Input Logic High Current, IIH
CLK, DFS, OE, VIH = 5V
-10.0
-
+10.0
µA
Input Logic Low Current, IIL
CLK, DFS, OE, VIL = 0V
-10.0
-
+10.0
µA
Input Capacitance, CIN
-7
-
pF
DIGITAL OUTPUTS
Output Logic High Voltage, VOH
IOH = 100µA; DVCC2 = 5V
4.0
-
-
V
Output Logic Low Voltage, VOL
IOL = 100µA; DVCC2 = 5V
-
-
0.8
V
Output Three-State Leakage Current, IOZ
VO = 0/5V; DVCC2 = 5V
-10
±110
µA
Output Logic High Voltage, VOH
IOH = 100µA; DVCC2 = 3V
2.4
-
-
V
Output Logic Low Voltage, VOL
IOL = 100µA; DVCC2 = 3V
-
-
0.5
V
Output Three-State Leakage Current, IOZ
VO = 0/5V; DVCC2 = 3V
-10
±110
µA
Output Capacitance, COUT
-10
-
pF
TIMING CHARACTERISTICS
Aperture Delay, tAP
-5
-
ns
Aperture Jitter, tAJ
-5
-
psRMS
Data Output Hold, tH
-5
-
ns
Data Output Delay, tOD
-6
-
ns
Data Output Enable Time, tEN
-5
-
ns
Data Output Enable Time, tDIS
-5
-
ns
Data Latency, tLAT
For a Valid Sample (Note 2)
-
-
7
Cycles
Power-Up Initialization
Data Invalid Time (Note 2)
-
-
20
Cycles
Sample Clock Pulse Width (Low)
fS = 60MSPS
7.5
8.33
-
ns
Sample Clock Pulse Width (High)
fS = 60MSPS
7.5
8.33
-
ns
Sample Clock Duty Cycle Variation
fS = 60MSPS
-
±5-
%
POWER SUPPLY CHARACTERISTICS
Analog Supply Voltage, AVCC
4.75
5.0
5.25
V
Digital Supply Voltage, DVCC1
4.75
5.0
5.25
V
Digital Output Supply Voltage, DVCC2
At 3.0V
2.7
3.0
3.3
V
At 5.0V
4.75
5.0
5.25
V
Total Supply Current, ICC
fIN = 10MHz and DFS = “0”
-
70
92
mA
Analog Supply Current, AICC
fIN = 10MHz and DFS = “0”
-
47
63
mA
Digital Supply Current, DICC
fIN = 10MHz and DFS = “0”
-
21
25
mA
Output Supply Current, DICC2
fIN = 10MHz and DFS = “0”
-
2
4
mA
Power Dissipation
fIN = 10MHz and DFS = “0”
-
346
452
mW
Offset Error Sensitivity,
∆VOS
AVCC or DVCC = 5V ±5%
-
±0.175
-
LSB
Gain Error Sensitivity,
∆FSE
AVCC or DVCC = 5V ±5%
-
±0.025
-
LSB
NOTES:
2. Parameter guaranteed by design or characterization and not production tested.
3. With the clock low and DC input.
Electrical Specifications
AVCC = DVCC1 = 5.0V, DVCC2 = 3.0V; VREFIN = VREFOUT; fS = 60MSPS at 50% Duty Cycle;
CL = 10pF; TA = 25
oC; Differential Analog Input; Typical Values are Test Results at 25oC,
Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
HI5667


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