94

The ultra high speed performance of the HFA5253 is a result

of UHF1 process leverages: low parasitic collector-to-

substrate capacitance of the bonded wafer, low collector-to-

base parasitic capacitance of the self-aligned base/emitter

poly-silicon transistors.

Definition of Terms

OFFSET VOLTAGE

Offset Voltage is the DC error between the voltage placed on

+7.5V.

GAIN

Gain is defined as the ratio of output voltage change to

-2.5V:

the effects of Interaction and End Point Nonlinearities.

LINEARITY ERROR

Linearity Error is a measure of output voltage worst case

deviation from a straight line that has been corrected for

offset and 7.5V Gain. Linearity Error is given as a

percentage of fullscale and is done in two ranges, 5V and

10.5V. DATA is measure at 0.5V steps from -2.5V to 8V for

equation is as follows for 10.5V fullscale:

The Linearity Error equation is as follows for 5V fullscale:

Linearity Error is calculated for every data point in the range

and the worst case value is recorded.

Speed Advantage

Harris Pin Drivers on bonded-wafer technology definitely have

a speed advantage, coming from the low collector-to-

addition, the patented switching stage which fits uniquely to

Harris’ UHF1 process is another big contributor for the high

speed. This switching circuitry requires low series-resistance

NPN and PNP transdiodes available in UHF1. The rise and

fall times of the pin driver are largely determined by the slew

rate at the node VSO in the Schematic. The dominant

mechanism for the slew rate is the charging/discharging of the

collector-base capacitors of the transistors connected to the

node VSO. The charging/discharging currents are coming

from the switching stage current sources. The fast rise and fall

times are achieved because of the negligible collector-to-

substrate capacitance and the small base-collector

capacitance due to the self-aligned recessed oxide [2].

The DATA/DATA differential stage is not a factor for the speed if

its current sources have enough current not to bottleneck the

transient. However it should be noted that the propagation

delay mismatch is determined by this stage. Sufficient current is

allocated to the differential stage current sources to best match

the low-to-high and high-to-low transient propagation delays.

The specified load condition is a 16 inch 50

Ω SMA cable with a

5pF capacitor at the end of the cable. This load simulates a

typical ATE environment for a DUT (Device Under Test) with

high impedance (>1k

Ω) digital inputs. The rise/fall time for

the same circuit structure as shown in the Schematic, can be

made faster by trimming for a higher power supply current.

Currently the pin driver has rise/fall times of less than 1ns (10%

speed enhancement will be made if there is a market demand.

Basic ATE System Application

Figure 1 shows a pin driver in a typical per-pin ATE system. The

pin driver works closely with the Dual-Level Comparator and

the Active Load. When the DUT pin acts as an input waiting for

a series of digital signals, the pin driver becomes active with a

logic “0” applied on the HIZ pin and provides the DUT pin with

digital signals. When the DUT pin acts as an output, the pin

driver output will be in high impedance mode (HIZ) with a logic

V

V

() V

()

–

7.5

------------------------------------------------------------------------------------------------------------------

=

V

V

() V

()

–

7.5

-------------------------------------------------------------------------------------------------------------

=

Linearity Error

V

OUT

V

()

–

10.5

--------------------------------------------------------------

=

V

()

V

IN

Gain

×

Offset

+

=

Linearity Error

V

OUT

V

()

–

5

--------------------------------------------------------------

=

HFA5253