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HFA5253 Datasheet(PDF) 6 Page - Harris Corporation |
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HFA5253 Datasheet(HTML) 6 Page - Harris Corporation |
6 / 18 page 94 The ultra high speed performance of the HFA5253 is a result of UHF1 process leverages: low parasitic collector-to- substrate capacitance of the bonded wafer, low collector-to- base parasitic capacitance of the self-aligned base/emitter technology and ultra high fT NPN (8GHz) and PNP (5.5GHz) poly-silicon transistors. Definition of Terms VOH AND VOL Output High Voltage and Output Low Voltage. VOH is the voltage at VOUT when the HIZ input is low and the DATA input is high. VOL is the voltage at VOUT when HIZ is low and DATA is low. The VOH and VOL levels are set with the VHIGH and VLOW inputs respectively. OFFSET VOLTAGE Offset Voltage is the DC error between the voltage placed on VHIGH or VLOW and the resulting VOH and VOL. VHIGH Offset Voltage Error is obtained by measuring VOH with VHIGH set to 0V and VLOW set to -2.5V to minimize interaction effects. VLOW Offset Voltage Error is the measurement of VOL with VLOW set to 0V and VHIGH set to +7.5V. GAIN Gain is defined as the ratio of output voltage change to input voltage change for a defined range. VHIGH Gain is calculated with the following equation with VLOW fixed at -2.5V: VLOW Gain is calculated in a similar manner: VHIGH is held fixed at 7.5V. These Gain calculations minimize the effects of Interaction and End Point Nonlinearities. LINEARITY ERROR Linearity Error is a measure of output voltage worst case deviation from a straight line that has been corrected for offset and 7.5V Gain. Linearity Error is given as a percentage of fullscale and is done in two ranges, 5V and 10.5V. DATA is measure at 0.5V steps from -2.5V to 8V for VHIGH and -3V to 7.5V for VLOW. The Linearity Error equation is as follows for 10.5V fullscale: The Linearity Error equation is as follows for 5V fullscale: Linearity Error is calculated for every data point in the range and the worst case value is recorded. VHIGH TO VLOW INTERACTION VHIGH to VLOW Interaction is the change in VOUT (the active channel) due to the inactive channel. VHIGH Interaction is measured as the change in VOH from 1V as VLOW is moved from 0V to 750mV (VLOW is corrected for gain and offset errors). VLOW Interaction is measured as the change in VOL from 0V as VHIGH is moved from 1V to 250mV (with VHIGH corrected for gain and offset errors). The minimum recommended difference between VHIGH and VLOW for the HFA5253 is 250mV. Speed Advantage Harris Pin Drivers on bonded-wafer technology definitely have a speed advantage, coming from the low collector-to- substrate capacitance and the high fT of the transistors. In addition, the patented switching stage which fits uniquely to Harris’ UHF1 process is another big contributor for the high speed. This switching circuitry requires low series-resistance NPN and PNP transdiodes available in UHF1. The rise and fall times of the pin driver are largely determined by the slew rate at the node VSO in the Schematic. The dominant mechanism for the slew rate is the charging/discharging of the collector-base capacitors of the transistors connected to the node VSO. The charging/discharging currents are coming from the switching stage current sources. The fast rise and fall times are achieved because of the negligible collector-to- substrate capacitance and the small base-collector capacitance due to the self-aligned recessed oxide [2]. The DATA/DATA differential stage is not a factor for the speed if its current sources have enough current not to bottleneck the transient. However it should be noted that the propagation delay mismatch is determined by this stage. Sufficient current is allocated to the differential stage current sources to best match the low-to-high and high-to-low transient propagation delays. The specified load condition is a 16 inch 50 Ω SMA cable with a 5pF capacitor at the end of the cable. This load simulates a typical ATE environment for a DUT (Device Under Test) with high impedance (>1k Ω) digital inputs. The rise/fall time for HFA5253 with 5VP-P is typically 1.3ns. Pin drivers, built out of the same circuit structure as shown in the Schematic, can be made faster by trimming for a higher power supply current. Currently the pin driver has rise/fall times of less than 1ns (10% to 90% of 5VP-P) when ICC is trimmed to 125mA. Further speed enhancement will be made if there is a market demand. Basic ATE System Application Figure 1 shows a pin driver in a typical per-pin ATE system. The pin driver works closely with the Dual-Level Comparator and the Active Load. When the DUT pin acts as an input waiting for a series of digital signals, the pin driver becomes active with a logic “0” applied on the HIZ pin and provides the DUT pin with digital signals. When the DUT pin acts as an output, the pin driver output will be in high impedance mode (HIZ) with a logic V HIGHGAIN V OH VHIGHat 6.5V () V OH VHIGHat -1V () – 7.5 ------------------------------------------------------------------------------------------------------------------ = V LOWGAIN V OL VLOWat 6V () V OL VLOWat -1.5V () – 7.5 ------------------------------------------------------------------------------------------------------------- = Linearity Error V OUT V OUT ID EAL () – 10.5 -------------------------------------------------------------- = V OUT IDE AL () V IN Gain × Offset + = Linearity Error V OUT V OUT ID EAL () – 5 -------------------------------------------------------------- = HFA5253 |
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