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MC74VHC1GT04 Datasheet(PDF) 1 Page - ON Semiconductor |
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MC74VHC1GT04 Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 8 page © Semiconductor Components Industries, LLC, 1999 November, 1999 – Rev. 1 1 Publication Order Number: MC74VHC1GT04/D MC74VHC1GT04 Inverting Buffer / CMOS Logic Level Shifter with LSTTL–Compatible Inputs The MC74VHC1GT04 is a single gate inverting buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The device input is compatible with TTL–type input thresholds and the output has a full 5V CMOS level output swing. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic–level translator from 3.0V CMOS logic to 5.0V CMOS Logic or from 1.8V CMOS logic to 3.0V CMOS Logic while operating at the high–voltage power supply. The MC74VHC1GT04 input structure provides protection when voltages up to 7V are applied, regardless of the supply voltage. This allows the MC74VHC1GT04 to be used to interface 5V circuits to 3V circuits. The output structures also provide protection when VCC = 0V. These input and output structures help prevent device destruction caused by supply voltage – input/output voltage mismatch, battery backup, hot insertion, etc. • High Speed: tPD = 3.8ns (Typ) at VCC = 5V • Low Power Dissipation: ICC = 2µA (Max) at TA = 25°C • TTL–Compatible Inputs: VIL = 0.8V; VIH = 2.0V • CMOS–CompatibleOutputs: VOH>0.8VCC;VOL<0.1VCC@Load • Power Down Protection Provided on Inputs and Outputs • Balanced Propagation Delays • Pin and Function Compatible with Other Standard Logic Families • Latchup Performance Exceeds 300mA • ESD Performance: HBM > 1500V; MM > 200V Figure 1. 5–Lead SOT–353 Pinout (Top View) IN A OUT Y 1 5 1 2 4 3 VCC NC IN A OUT Y GND LOGIC SYMBOL SC–88A / SOT–353 DF SUFFIX CASE 419A PIN ASSIGNMENT 1 2 3 GND NC IN A http://onsemi.com Pin 1 d = Date Code VKd 4 5 VCC OUT Y FUNCTION TABLE MARKING DIAGRAM See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. ORDERING INFORMATION L H A Input Y Output H L |
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