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CD4086BMS Datasheet(PDF) 1 Page - Intersil Corporation

Part No. CD4086BMS
Description  CMOS Expandable 4-Wide 2-Input AND-OR-INVERT Gate
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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CD4086BMS Datasheet(HTML) 1 Page - Intersil Corporation

   
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7-1055
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
CD4086BMS
CMOS Expandable 4-Wide 2-Input
AND-OR-INVERT Gate
Pinout
CD4086BMS
TOP VIEW
Functional Diagram
A
B
J = INH + ENABLE +
NC
E
F
VSS
VDD
D
C
ENABLE/EXP
INHIBIT/EXP
H
G
1
2
3
4
5
6
7
14
13
12
11
10
9
8
AB + CD + EF + GH
NC = NO CONNECTION
10 INHIBIT/EXP
A
B
C
D
E
F
G
H
11
J = INH + ENABLE + AB + CD + EF + GH
ENABLE/EXP
1
2
12
13
5
6
8
9
3
J
LOGIC 1
≡ HIGH
LOGIC 0
≡ LOW
VDD = 14
VSS = 7
NC = 4
Features
• Medium Speed Operation - tPHL = 90ns; tPLH = 140ns
(Typ.) at 10V
• High Voltage Type (20V Rating)
• INHIBIT and ENABLE Inputs
• Buffered Outputs
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1
µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Description
CD4086BMS contains one 4-wide 2-input AND-OR-INVERT
gate with an INHIBIT/EXP input and an ENABLE/EXP input.
For a 4-wide A-O-I function INHIBIT/EXP is tied to VSS and
ENABLE/EXP to VDD. See Figure 2 and its associated
explanation for applications where a capability greater than
4-wide is required.
The CD4076B is supplied in these 14 lead outline packages:
Braze Seal DIP
H4H
Frit Seal DIP
H1B
Ceramic Flatpack
H4F
December 1992
File Number
3328


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