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CD4035BMS Datasheet(PDF) 6 Page - Intersil Corporation

Part No. CD4035BMS
Description  CMOS 4 -Stage Parallel In/Parallel Out Shift Register
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CD4035BMS Datasheet(HTML) 6 Page - Intersil Corporation

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7-856
Specifications CD4035BMS
Logic Diagram
FIGURE 1. TYPICAL STAGE DETAIL LOGIC
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K
± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K
± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V
± 0.5V
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
FUNCTION
OPEN
GROUND
VDD
9V
± -0.5V
OSCILLATOR
50kHz
25kHz
9
7
*
3
*
K
4
*
J
PS
PS
PS
T
T
p
n
PS
p
n
PS
p
n
CL
CL
p
n
*ALL INPUTS PROTECTED
BY CMOS INPUT
PROTECTION NETWORK
*
D
CL
Q
Q
R
P
PS
5
*
6
*
10
*
D
CL
Q
Q
R
P
PS
T
T
p
n
T
T
p
n
T
T
p
n
11
*
D
CL
Q
Q
R
P
PS
T
T
p
n
T
T
p
n
12
*
D
CL
Q
Q
R
P
PS
T
T
p
n
T
T
p
n
CL
CL
p
n
CL
CL
p
n
PS
CL
CL
p
n
Q
Q
R
P
D
CL
CL
CL
T
T
2
*
TRUE/COMPLEMENT
D
CL
Q
Q
R
P
PS
1
Q1/Q1
15
Q2/Q2
14
Q3/Q3
13
Q4/Q4
VDD
VSS
PARALLEL/
SERIAL CONTROL
CLOCK
RESET
P/S = 0 = SERIAL MODE
T/C = 1= TRUE OUTPUTS


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