NBLVEP16VR

http://onsemi.com

2

Q

Q

D

D

OD_MODE

EN

Figure 2. Logic Diagram

CS_SEL

QHG

QHG

EN_SEL

Q

Q

0

1

LVCMOS/LVTTL

Threshold

470

W

470

W

10 mA ea. (opt.)

4 mA ea.

4 mA ea. (opt.)

LEN

LATCH

Q

D

Table 1. Q AND Q INTERNAL CURRENT SOURCE

SELECTOR

CS_SEL

Q

Q

See Figure

OPEN

4 mA Typical

4 mA Typical

13, 13

8 mA Typical

8 mA Typical

10, 13

0 mA

4 mA Typical

13, 13

Table 2. QHG AND QHG INTERNAL CURRENT

SOURCE SELECTOR

QHG

QHG

See Figure

OPEN

0 mA

0 mA

8, 11

10 mA Typical

10 mA Typical

9, 12

Table 3. OUTPUT ENABLE AND OUTPUT DISABLED STATE TRUTH TABLE

OD−MODE*

EN*

Q and Q

QHG

QHG

Low or OPEN

Data

Data

Data

Low or OPEN

Data

Low

High

Low or OPEN

Data

Low

High

Low or OPEN

Data

Data

Data

High

Data

Data

Data

High

Data

High

Low

High

Data

High

Low

High

Data

Data

Data

*Pins will default LOW when left open.

†Pin will default HIGH when left open.