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SCAN182541ASSC Datasheet(PDF) 3 Page - Fairchild Semiconductor |
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SCAN182541ASSC Datasheet(HTML) 3 Page - Fairchild Semiconductor |
3 / 11 page 3 www.fairchildsemi.com Description of BOUNDARY-SCAN Circuitry The scan cells used in the BOUNDARY-SCAN register are one of the following two types depending upon their loca- tion. Scan cell TYPE1 is intended to solely observe system data, while TYPE2 has the additional ability to control sys- tem data. Scan cell TYPE1 is located on each system input pin while scan cell TYPE2 is located at each system output pin as well as at each of the two internal active-high output enable signals. AOE controls the activity of the A-outputs while BOE controls the activity of the B-outputs. Each will acti- vate their respective outputs by loading a logic high. The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low. Bypass Register Scan Chain Definition Logic 0 SCAN182541A Product IDCODE (32-Bit Code per IEEE 1149.1) The INSTRUCTION register is an 8-bit register which cap- tures the default value of 10000001 (SAMPLE/PRELOAD) during the CAPTURE-IR instruction command. The benefit of capturing SAMPLE/PRELOAD as the default instruction during CAPTURE-IR is that the user is no longer required to shift in the 8-bit instruction for SAMPLE/PRELOAD. The sequence of: CAPTURE-IR →EXIT1-IR→ UPDATE-IR will update the SAMPLE/PRELOAD instruction. For more infor- mation refer to the section on instruction definitions. Instruction Register Scan Chain Definition MSB →LSB Scan Cell TYPE1 Scan Cell TYPE2 Version Entity Part Manufacture r Required b y Number ID 1149.1 0000 111111 000000100 1 00000001111 1 MSB LSB Instruction Code Instruction 00000000 EXTEST 10000001 SAMPLE/PRELOAD 10000010 CLAMP 00000011 HIGH-Z 01000001 SAMPLE-IN 01000010 SAMPLE-OUT 00100010 EXTEST-OUT 10101010 IDCODE 11111111 BYPASS All Others BYPASS |
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