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CY7C1316AV18
CY7C1318AV18
CY7C1320AV18
Document #: 38-05499 Rev. *B
Page 11 of 20
tCQOH
tCHCQX
Echo Clock Hold after C/C Clock Rise
–0.45
–
–0.45
–
–0.50
–
ns
tCQD
tCQHQV
Echo Clock High to Data Valid
–
0.30
–
0.35
–
0.40
ns
tCQDOH
tCQHQX
Echo Clock High to Data Invalid
–0.30
–
–0.35
–
–0.40
–
ns
tCHZ
tCHZ
Clock (C and C) Rise to High-Z (Active to High-Z)[19, 20]
–0.45–
0.45
–
0.50
ns
tCLZ
tCLZ
Clock (C and C) Rise to Low-Z[19, 20]
–0.45
–
–0.45
–
–0.50
–
ns
DLL Timing
tKC Var
tKC Var
Clock Phase Jitter
–
0.20
–
0.20
–
0.20
ns
tKC lock
tKC lock
DLL Lock Time (K, C)
1024
–
1024
–
1024
–
Cycles
tKC Reset
tKC Reset
K Static to DLL Reset
30
30
30
ns
Switching Characteristics Over the Operating Range (continued)[17,18]
Cypress
Parameter
Consortium
Parameter
Description
250 MHz
200 MHz
167 MHz
Unit
Min. Max. Min. Max.
Min.
Max.
Switching Waveforms[21, 22, 23]
Notes:
19. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
20. At any given voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
21. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1.
22. Output are disabled (High-Z) one clock cycle after a NOP.
23. In this example, if address A2 = A1,then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.
K
1
23456
7
8910
K
LD
R/W
A
DQ
C
C#
READ
READ
READ
NOP
NOP
WRITE
WRITE
Q40
tKH
tKHKH
tKHCH
tCO
tKL
tCYC
t
tHC
tSA
tHA
tSD
tHD
tKHCH
NOP
tSD
tHD
DON’T CARE
UNDEFINED
tCLZ
tDOH
tCHZ
SC
tKH
tKHKH
tKL
tCYC
A0
D20
D21
D30
D31
Q00
Q11
Q01
Q10
Qx2
tCO
tCQD
tDOH
A1
A2
A3
A4
Q41
CQ
CQ#
tCCQO
tCQOH
tCCQO
tCQOH
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