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MC68030FE33 Datasheet(PDF) 27 Page - Motorola, Inc

Part No. MC68030FE33
Description  ENHANCED 32-BIT MICROPROCESSOR
Download  602 Pages
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Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com
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MC68030FE33 Datasheet(HTML) 27 Page - Motorola, Inc

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Introduction
1-4
MC68030 USER’S MANUAL
MOTOROLA
1.2 MC68030 EXTENSIONS TO THE M68000 FAMILY
In addition to the on-chip instruction cache present in the MC68020, the MC68030 has an
internal data cache. Data that is accessed during read cycles may be stored in the on-chip
cache, where it is available for subsequent accesses. The data cache reduces the number
of external bus cycles when the data operand required by an instruction is already in the
data cache.
Performance is enhanced further because the on-chip caches can be internally accessed in
a single clock cycle. In addition, the bus controller provides a two-clock cycle synchronous
mode and burst mode accesses that can transfer data in as little as one clock per long word.
The MC68030 enhanced microprocessor contains an on-chip MMU that allows address
translation to operate in parallel with the CPU core, the internal caches, and the bus
controller.
Additional signals support emulation and system analysis. External debug equipment can
disable the on-chip caches and the MMU to freeze the MC68030 internal state during
breakpoint processing. In addition, the MC68030 indicates:
1. The start of a refill of the instruction pipe
2. Instruction boundaries
3. Pending trace or interrupt processing
4. Exception processing
5. Halt conditions
This status and control information allows external debugging equipment to trace the
MC68030 activity and interact nonintrusively with the MC68030 to effectively reduce system
debug effort.
1.3 PROGRAMMING MODEL
The programming model of the MC68030 consists of two groups of registers: the user model
and the supervisor model. This corresponds to the user and supervisor privilege levels. User
programs executing at the user privilege level use the registers of the user model. System
software executing at the supervisor level uses the control registers of the supervisor level
to perform supervisor functions.


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