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MC68030FE33 Datasheet(PDF) 26 Page - Motorola, Inc

Part No. MC68030FE33
Description  ENHANCED 32-BIT MICROPROCESSOR
Download  602 Pages
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Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com
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MC68030FE33 Datasheet(HTML) 26 Page - Motorola, Inc

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Introduction
MOTOROLA
MC68030 USER’S MANUAL
1-3
1.1 FEATURES
The features of the MC68030 microprocessor are:
• Object Code Compatible with the MC68020 and Earlier M68000 Microprocessors
• Complete 32-Bit Nonmultiplexed Address and Data Buses
• 16 32-Bit General-Purpose Data and Address Registers
• Two 32-Bit Supervisor Stack Pointers and 10 Special-Purpose Control Registers
• 256-Byte Instruction Cache and 256-Byte Data Cache Can Be Accessed Simulta-
neously
• Paged MMU that Translates Addresses in Parallel with Instruction Execution and Inter-
nal Cache Accesses
• Two Transparent Segments Allow Untranslated Access to Physical Memory To Be D
fined for Systems That Transfer Large Blocks of Data between Predefined Physical Ad-
dresses — e.g., Graphics Applications
• Pipelined Architecture with Increased Parallelism Allows Accesses to Internal Caches
To Occur in Parallel with Bus Transfers and Instruction Execution To Be Overlapped
• Enhanced Bus Controller Supports Asynchronous Bus Cycles (three clocks minimum),
Synchronous Bus Cycles (two clocks minimum), and Burst Data Transfers (one clock
minimum) all to the Physical Address Space
• Dynamic Bus Sizing Supports 8-, 16-, 32-Bit Memories and Peripherals
• Support for Coprocessors with the M68000 Coprocessor Interface — e.g., Full IEEE
Floating-Point Support Provided by the MC68881/MC68882 Floating-Point Coproces-
sors
• 4-Gbyte Logical and Physical Addressing Range
• Implemented in Motorola's HCMOS Technology That Allows CMOS and HMOS (High-
Density NMOS) Gates to be Combined for Maximum Speed, Low Power, and Optimum
Die Size
• Processor Speeds Beyond 20 MHz
Both improved performance and increased functionality result from the on-chip
implementation of the MMU and the data and instruction caches. The enhanced bus
controller and the internal parallelism also provide increased system performance. Finally,
the improved bus interface, the reduction in physical size, and the lower power consumption
combine to reduce system costs and satisfy cost/performance goals of the system designer.


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