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FSBM20SM60A Datasheet(PDF) 13 Page - Fairchild Semiconductor

Part No. FSBM20SM60A
Description  SPM (Smart Power Module)
Download  16 Pages
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Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FSBM20SM60A Datasheet(HTML) 13 Page - Fairchild Semiconductor

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©2003 Fairchild Semiconductor Corporation
Rev. E, August 2003
Note:
1) It would be recommended that by-pass capacitors for the gating input signals, IN(UL), IN(VL), IN(WL), IN(UH), IN(VH) and IN(WH) should be placed on the SPM pins
and on the both sides of CPU and SPM for the fault output signal, VFO, as close as possible.
2) The logic input is compatible with standard CMOS or LSTTL outputs.
3) RPLCPL/RPHCPH/RPFCPF coupling at each SPM input is recommended in order to prevent input/output signals’ oscillation and it should be as close as possible to
each of SPM pins.
Fig. 12. Recommended CPU I/O Interface Circuit
Note:
It would be recommended that the bootstrap diode, DBS, has soft and fast recovery characteristics.
Fig. 13. Recommended Bootstrap Operation Circuit and Parameters
CPU
COM
5V-Line
1.2nF
0.47nF
1nF
4.7k
4.7k
,,
IN (UL) IN (VL) IN
(WL)
,,
IN
(UH)
IN
(VH)
IN(WH)
VFO
100
100
100
1nF
SPM
2k
R
PF
R
PL
R
PH
C
PF
C
PL
C
PH
15V-Line
20
47uF
0.1uF
470uF
0.1uF
One-Leg Diagram of SPM
Vcc
IN
COM
VB
HO
VS
Vcc
IN
COM
OUT
Inverter
Output
P
N
These Values depend on PW M Control Algorithm
D
BS


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