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TPS7H4001-SP Datasheet(PDF) 24 Page - Texas Instruments |
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TPS7H4001-SP Datasheet(HTML) 24 Page - Texas Instruments |
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24 / 48 page  tSS :ms; = 0.8 × CSS (nF) × VREF (V) ISS (µA) 24 TPS7H4001-SP SLVSEN7 – APRIL 2020 www.ti.com Product Folder Links: TPS7H4001-SP Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Feature Description (continued) Table 1. Switching Frequency, SYNC, and RT Pin Usage Table MODE RT PIN SYNC1 PIN SYNC2 PIN SWITCHING FREQUENCY Internal oscillator Resistor to GND based on Figure 51 Floating GND Configurable using internal oscillator from 100 kHz to 1 MHz depending on RT resistor value External synchronization External input clock GND Internally synchronized and 180° out of phase with external clock input from 100 kHz to 1 MHz VIN Internally synchronized and in phase with external clock input from 100 kHz to 1 MHz Master Float Outputs 500-kHz clock in phase with internal switching frequency Outputs 500-kHz clock at 90° out of phase with internal switching frequency 500 kHz 7.3.8 Soft-Start (SS/TR) The device uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the reference voltage and regulates the output accordingly. A CSS capacitor on the SS/TR pin to GND implements a soft-start time. Equation 5 shows the equation for the nominal soft-start time, tSS. This is the time it will take VOUT to go from 10% to 90% of the programmed voltage. The voltage reference (VREF) is 0.604 V and the soft-start charge current (ISS) is 2.5 µA. When calculating the soft-start time tSS, it is important to take into account the variation of the parameters CSS, VREF, and ISS as these may cause tSS to deviate from the nominal value in the actual implementation. (5) When any of the following four scenarios occur the SS/TR pin is discharged: • the input UVLO is triggered, • the EN pin is pulled below 1.05 V, • the high-side switch current limit threshold is exceeded, or • a thermal shutdown event occurs. With the exception of the scenario where the high-side current limit threshold is exceeded, the device will then stop switching and enter into low current operation. At the subsequent power-up, when the shutdown condition is removed, the device does not start switching until it has discharged its SS/TR pin to ground ensuring proper soft- start behavior. The device will enter into a pulse-skipping mode during start-up in the event that VSENSE is greater than the voltage at the SS/TR pin. During this period, the high-side switch will remain off and the low-side switch will remain on until VSENSE again falls below the voltage at SS/TR. |
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