INGAM386SXL-25 datasheet(10/30 Pages) AMD

Part #	INGAM386SXL-25

Description	High-Performance, Low-Power, Embedded Microprocessors

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Manufacturer	AMD [Advanced Micro Devices]

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10

Am386SX/SXL/SXLV Microprocessors Data Sheet

FINAL

PIN DESCRIPTIONS

A23–A1

Address Bus (Outputs)

Outputs physical memory or port I/O addresses.

ADS

Address Status (Active Low; Output)

Indicates that a valid bus cycle definition and address

(W/R, D/C, M/IO, BHE, BLE, and A23–A1) are being

driven at the Am386SX/SXL/SXLV microprocessor

pins. Bus cycles initiated by ADS must be terminated

by READY.

BHE, BLE

Byte Enables (Active Low; Outputs)

Indicate which data bytes of the data bus take part in a

bus cycle.

BUSY

Busy (Active Low; Input)

Signals a busy condition from a processor extension.

BUSY has an internal pull-up resistor.

CLK2

CLK2 (Input)

Provides the fundamental timing for the Am386SX/

SXL/SXLV microprocessor.

D15–D0

Data Bus (Inputs/Outputs)

Inputs data during memory, I/O, and interrupt acknowl-

edge read cycles; outputs data during memory and I/O

write cycles.

D/C

Data/Control (Output)

A bus cycle definition pin that distinguishes data cy-

cles, either memory or I/O, from control cycles which

are interrupt acknowledge, halt, and code fetch.

ERROR

Error (Active Low; Input)

Signals an error condition from a processor extension.

ERROR has an internal pull-up resistor.

FLT

Float (Active Low; Input)

An input which forces all bidirectional and output sig-

nals, including HLDA, to the three-state condition. FLT

has an internal pull-up resistor. The pin, if not used,

should be disconnected.

HLDA

Bus Hold Acknowledge (Active High; Output)

Output indicates that the Am386SX/SXL/SXLV micro-

processor has surrendered control of its logical bus to

another bus master.

HOLD

Bus Hold Request (Active High; Input)

Input allows another bus master to request control of

the local bus.

IIBEN (Am386SXLV Only)

I/O Instruction Break Enable (Active Low; Input)

Enables the I/O instruction break feature. IIBEN has a

dynamic internal pull-up resistor. The IIBEN pull-up is

active during RESET and whenever the signal is not

driven active Low by the system.

INTR

Interrupt Request (Active High; Input)

A maskable input that signals the Am386SX/SXL/

SXLV microprocessor to suspend execution of the cur-

rent program and execute an interrupt acknowledge

function.

LOCK

Bus Lock (Active Low; Output)

A bus cycle definition pin that indicates that other sys-

tem bus masters are not to gain control of the system

bus while it is active.

M/IO

Memory/IO (Output)

A bus cycle definition pin that distinguishes memory cy-

cles from input/output cycles.

NA

Next Address (Active Low; Input)

Used to request address pipelining.

NC

No Connect

Should always be left unconnected. Connection of an

NC pin may cause the processor to malfunction or be

incompatible with future steppings of the Am386SX/

SXL/SXLV microprocessor.

NMI

Non-Maskable Interrupt Request

(Active High; Input)

A non-maskable input that signals to the Am386SX/

SXL/SXLV microprocessor to suspend execution of the

current program and execute an interrupt acknowledge

function.

PEREQ

Processor Extension Request (Active High; Input)

Indicates that the processor has data to be transferred

by the Am386SX/SXL/SXLV microprocessor. PEREQ

has an internal pull-down resistor.

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