DDR SDRAM

DDR SDRAM 256Mb E-die (x4, x8) Pb-Free

Rev. 1.1 October, 2004

Command Truth Table

(V=Valid, X=Don

′t Care, H=Logic High, L=Logic Low)

COMMAND

CKEn-1 CKEn

CS

RAS

CAS

WE

BA0,1 A10/AP

A0 ~ A9,

A11,A12

Note

Register

Extended MRS

H

X

L

L

L

L

OP CODE

1, 2

Register

Mode Register Set

H

X

L

L

L

L

OP CODE

1, 2

Refresh

Auto Refresh

H

H

LL

L

H

X

3

Self

Refresh

Entry

L

3

Exit

L

H

LH

H

H

X

3

HX

X

X

3

Bank Active & Row Addr.

H

X

L

L

H

H

V

Row Address

Read &

Column Address

Auto Precharge Disable

HX

L

H

L

H

V

L

Column

Address

4

Auto Precharge Enable

H

4

Write &

Column Address

Auto Precharge Disable

HX

L

H

L

L

V

L

Column

Address

4

Auto Precharge Enable

H

4, 6

Burst Stop

H

X

L

H

H

L

X

7

Precharge

Bank Selection

HX

L

L

H

L

VL

X

All Banks

X

H

5

Active Power Down

Entry

H

L

HX

X

X

X

LV

V

V

Exit

L

H

X

X

X

X

Precharge Power Down Mode

Entry

H

L

HX

X

X

X

LH

H

H

Exit

L

H

HX

X

X

LV

V

V

DM(UDM/LDM for x16 only)

H

X

X

8

No operation (NOP) : Not defined

H

X

HX

X

X

X

9

LH

H

H

9

2. EMRS/MRS can be issued only at all banks precharge state.

A new command can be issued 2 clock cycles after EMRS or MRS.

3. Auto refresh functions are same as the CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

6. During burst write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

7. Burst stop command is valid at every burst length.

8. DM(x4/8) sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).

9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.

Note :