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ZL50015 Datasheet(PDF) 68 Page - Zarlink Semiconductor Inc |
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ZL50015 Datasheet(HTML) 68 Page - Zarlink Semiconductor Inc |
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68 / 122 page  ZL50015 Data Sheet 68 Zarlink Semiconductor Inc. Table 32 - Lock Detector Interval Register (LDIR) Bits Bit Name Description 15 - 0 LDT15 - 0 Lock Detect Threshold Bits The binary value of these bits defines the upper limit of the absolute phase from the phase detector output for lock detection. When the value of the absolute phase is less than or equal to LDT for duration of time defined by the LDIR register, the DPLL locks. When the value of the absolute phase is greater than LDT for duration of time defined by the LDIR register divided by 256, the DPLL does not lock. Note: LDT should be calculated as per the maximum expected amplitude of jitter on the active input reference using the following formula: LDT = MAX_EXP_JITTER (ns) x 2 15.2 (ns) Example: If maximum expected jitter amplitude on 2.048 MHz reference is 10UI (i.e., 10 x 488.2 ns = 4882 ns) (assuming the jitter frequency where DPLL attenuation is big), the LDT should be programmed to be (4882/15.2) x 2 = 642 = 0282H Table 31 - Lock Detector Threshold Register (LDTR) Bits Bit Name Description 15 - 0 LDI15 - 0 Lock Detector Interval Bits The binary value of these bits defines the time interval that the output phase detector must be below the lock detect threshold to declare lock. Unsigned representation of the LDI bits is defined in 4 ms intervals. External Read/Write Address: 0047H Reset Value: 000FH 15 14 13 12 11 10 98 7654 321 0 LDT 15 LDT 14 LDT 13 LDT 12 LDT 11 LDT 10 LDT 9 LDT 8 LDT 7 LDT 6 LDT 5 LDT 4 LDT 3 LDT 2 LDT 1 LDT 0 External Read/Write Address: 0048H Reset Value: 2C00H 15 14 13 12 11 10 98 7654 321 0 LDI 15 LDI 14 LDI 13 LDI 12 LDI 11 LDI 10 LDI 9 LDI 8 LDI 7 LDI 6 LDI 5 LDI 4 LDI 3 LDI 2 LDI 1 LDI 0 |
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