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5962F9583401QXA Datasheet(PDF) 2 Page - Aeroflex Circuit Technology

Part # 5962F9583401QXA
Description  Quad Receiver
Download  11 Pages
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Manufacturer  AEROFLEX [Aeroflex Circuit Technology]
Direct Link  http://www.aeroflex.com
Logo AEROFLEX - Aeroflex Circuit Technology

5962F9583401QXA Datasheet(HTML) 2 Page - Aeroflex Circuit Technology

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2
TRUTH TABLE
PIN DESCRIPTION
APPLICATIONS INFORMATION
The UT54LVDS032 receiver’s intended use is primarily in an
uncomplicated point-to-point configuration as is shown in
Figure 3. This configuration provides a clean signaling
environment for quick edge rates of the drivers. The receiver is
connected to the driver through a balanced media which may be
a standard twisted pair cable, a parallel pair cable, or simply
PCB traces. Typically, the characteristic impedance of the media
is in the range of 100
Ω. A termination resistor of 100Ω should
be selected to match the media and is located as close to the
receiver input pins as possible. The termination resistor converts
the current sourced by the driver into voltages that are detected
by the receiver. Other configurations are possible such as a
multi-receiver configuration, but the effects of a mid-stream
connector(s), cable stub(s), and other impedance discontinuities,
as well as ground shifting, noise margin limits, and total
termination loading must be taken into account.
The UT54LVDS032 differential line receiver is capable of
detecting signals as low as 100mV, over a + 1V common-mode
range centered around +1.2V. This is related to the driver offset
voltage which is typically +1.2V. The driven signal is centered
around this voltage and may shift +1V around this center point.
The +1V shifting may be the result of a ground potential
difference between the driver’s ground reference and the
receiver’s ground reference, the common-mode effects of
coupled noise or a combination of the two. Both receiver input
pins should honor their specified operating input voltage range
of 0V to +2.4V (measured from each pin to ground).
Enables
Input
Output
EN
EN
R
IN+ - RIN-
R
OUT
L
H
X
Z
All other combinations
of ENABLE inputs
VID > 0.1V
H
V
ID < -0.1V
L
Full Fail-safe
OPEN/SHORT or
Terminated
H
Pin No.
Name
Description
2, 6, 10, 14
R
IN+
Non-inverting receiver input pin
1, 7, 9, 15
RIN-
Inverting receiver input pin
3, 5, 11, 13
ROUT
Receiver output pin
4
EN
Active high enable pin, OR-ed
with EN
12
EN
Active low enable pin, OR-ed
with EN
16
V
DD
Power supply pin, +5V + 10%
8
V
SS
Ground pin
Figure 2. UT54LVDS032 Pinout
UT54LVDS032
Receiver
16
15
14
13
12
11
10
9
VDD
R IN4-
RIN4+
ROUT4
EN
ROUT3
RIN3+
RIN3-
1
RIN1-
2
R IN1+
3
ROUT1
4
EN
5
ROUT2
6
RIN2+
7
RIN2-
8
VSS
ENABLE
DATA
INPUT
1/4 UT54LVDS031
1/4 UT54LVDS032
+
-
DATA
OUTPUT
Figure 3. Point-to-Point Application
RT 100


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