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MC74HCT573A Datasheet(PDF) 1 Page - ON Semiconductor |
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MC74HCT573A Datasheet(HTML) 1 Page - ON Semiconductor |
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© Semiconductor Components Industries, LLC, 2000 March, 2000 – Rev. 8 1 Publication Order Number: MC74HCT573A/D MC74HCT573A Octal 3-State Noninverting Transparent Latch with LSTTL Compatible Inputs High–Performance Silicon–Gate CMOS The MC74HCT573A is identical in pinout to the LS573. This device may be used as a level converter for interfacing TTL or NMOS outputs to High–Speed CMOS inputs. These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold times becomes latched. The Output Enable input does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the high–impedance state. Thus, data may be latched even when the outputs are not enabled. The HCT573A is identical in function to the HCT373A but has the Data Inputs on the opposite side of the package from the outputs to facilitate PC board layout. • Output Drive Capability: 15 LSTTL Loads • TTL/NMOS–Compatible Input Levels • Outputs Directly Interface to CMOS, NMOS and TTL • Operating Voltage Range: 4.5 to 5.5 V • Low Input Current: 10 µA • In Compliance with the Requirements Defined by JEDEC Standard No. 7A • Chip Complexity: 234 FETs or 58.5 Equivalent Gates — Improved Propagation Delays — 50% Lower Quiescent Power http://onsemi.com MARKING DIAGRAMS 1 20 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week SOIC WIDE–20 DW SUFFIX CASE 751D HCT573A AWLYYWW PDIP–20 N SUFFIX CASE 738 1 20 MC74HCT573AN AWLYYWW TSSOP–20 DT SUFFIX CASE 948G 1 20 1 20 1 20 Device Package Shipping ORDERING INFORMATION MC74HCT573AN PDIP–20 1440 / Box MC74HCT573ADW SOIC–WIDE 38 / Rail MC74HCT573ADWR2 SOIC–WIDE 1000 / Reel MC74HCT573ADT TSSOP–20 75 / Rail MC74HCT573ADTR2 TSSOP–20 2500 / Reel HCT 573A ALYW 1 20 |
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