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MC74HCT541A Datasheet(PDF) 1 Page - ON Semiconductor |
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MC74HCT541A Datasheet(HTML) 1 Page - ON Semiconductor |
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© Semiconductor Components Industries, LLC, 2000 March, 2000 – Rev. 2 1 Publication Order Number: MC74HCT541A/D MC74HCT541A Octal 3-State Non-Inverting Buffer/Line Driver/ Line Receiver With LSTTL-Compatible Inputs High–Performance Silicon–Gate CMOS The MC74HCT541A is identical in pinout to the LS541. This device may be used as a level converter for interfacing TTL or NMOS outputs to high speed CMOS inputs. The HCT541A is an octal non–inverting buffer/line driver/line receiver designed to be used with 3–state memory address drivers, clock drivers, and other bus–oriented systems. This device features inputs and outputs on opposite sides of the package and two ANDed active–low output enables. • Output Drive Capability: 15 LSTTL Loads • TTL/NMOS–Compatible Input Levels • Outputs Directly Interface to CMOS, NMOS and TTL • Operating Voltage Range: 4.5 to 5.5V • Low Input Current: 1µA • In Compliance With the JEDEC Standard No. 7A Requirements • Chip Complexity: 134 FETs or 33.5 Equivalent Gates 18 Y1 2 A1 17 Y2 3 A2 16 Y3 4 A3 15 Y4 5 A4 14 Y5 6 A5 13 Y6 7 A6 12 Y7 8 A7 11 Y8 9 A8 OE1 OE2 1 19 Output Enables Data Inputs Non–Inverting Outputs PIN 20 = VCC PIN 10 = GND LOGIC DIAGRAM Pinout: 20–Lead Packages (Top View) 19 20 18 17 16 15 14 2 1 3456 7 VCC 13 8 12 9 11 10 OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND L L H X L L X H L H X X FUNCTION TABLE Inputs Output Y OE1 OE2 A L H Z Z Z = High Impedance X = Don’t Care http://onsemi.com MARKING DIAGRAMS 1 20 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week SOIC WIDE–20 DW SUFFIX CASE 751D HCT541A AWLYYWW PDIP–20 N SUFFIX CASE 738 1 20 MC74HCT541AN AWLYYWW 1 20 1 20 Device Package Shipping ORDERING INFORMATION MC74HCT541AN PDIP–20 1440 / Box MC74HCT541ADW SOIC–WIDE 38 / Rail MC74HCT541ADWR2 SOIC–WIDE 1000 / Reel |
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