MC74HCT374A

http://onsemi.com

4

∆ICC

Additional Quiescent Supply

Current

Vin = 2.4 V, Any One Input

Vin = VCC or GND, Other Inputs

≥ –55_C

25

_C to 125_C

Current

Vin = VCC or GND, Other In uts

lout = 0 µA

5.5

2.9

2.4

mA

NOTE: 1. Total Supply Current = ICC + Σ∆ICC.

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book

(DL129/D).

Guaranteed Limit

Symbol

Parameter

– 55 to

25

_C

v 85_C

v 125_C

Unit

fmax

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 4)

30

24

20

MHz

tPLH,

tPHL

Maximum Propagation Delay, Clock to Q

(Figures 1 and 4)

31

39

47

ns

tPLZ,

tPHZ

Maximum Propagation Delay, Output Enable to Q

(Figures 2 and 5)

30

38

45

ns

tPZL,

tPZH

Maximum Propagation Delay, Output Enable to Q

(Figures 2 and 5)

30

38

45

ns

tTLH,

tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 4)

12

15

18

ns

Cin

Maximum Input Capacitance

10

10

10

pF

Cout

Maximum Three–State Output Capacitance

(Output in High–Impedance State)

15

15

15

pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON

Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25

°C, VCC = 5.0 V

CPD

Power Dissipation Capacitance (Per Flip–Flop)*

65

pF

* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

ON Semiconductor High–Speed CMOS Data Book (DL129/D).

Guaranteed Limit

Symbol

Parameter

– 55 to

25

_C

v 85_C

v 125_C

Unit

tsu

Minimum Setup Time, Data to Clock

(Figure 3)

12

15

18

ns

th

Minimum Hold Time, Clock to Data

(Figure 3)

5.0

5.0

5.0

ns

tw

Minimum Pulse Width, Clock

(Figure 1)

12

15

18

ns

tr, tf

Maximum Input Rise and Fall Times

(Figure 1)

500

500

500

ns