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IDT72V70210 Datasheet(PDF) 1 Page - Integrated Device Technology

Part No. IDT72V70210
Description  3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT72V70210 Datasheet(HTML) 1 Page - Integrated Device Technology

 
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2005 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-5714/4
JANUARY 2005
3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH
1,024 x 1,024
IDT72V70210
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. The ST-BUSis a trademari of Mitel Corp.
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
••••• 32 serial input and output streams
••••• 1,024 x 1,024 channel non-blocking switching at 2.048 Mb/s
••••• Per-channel Variable Delay Mode for low-latency applications
••••• Per-channel Constant Delay Mode for frame integrity applications
••••• Automatic identification of ST-BUS® and GCI serial streams
••••• Automatic frame offset delay measurement
••••• Per-stream frame delay offset programming
••••• Per-channel high impedance output control
••••• Per-channel processor mode to allow microprocessor writes to
TX streams
••••• Direct microprocessor access to all internal memories
••••• Memory block programming for quick set-up
••••• IEEE-1149.1 (JTAG) Test Port
••••• Internal Loopback for testing
•••••· Available in 144-pin Ball Grid Array (BGA) and 144-pin Thin Quad
Flatpack (TQFP) packages
••••• Operating Temperature Range -40
°°°°°C to +85°°°°°C
••••• 3.3V I/O with 5V tolerant inputs and TTL compatible outputs
DESCRIPTION:
The IDT72V70210 has a non-blocking switch capacity of 1,024 x 1,024
channels at 2.048 Mb/s. With 32 inputs and 32 outputs, programmable per
streamcontrol,andavarietyofoperatingmodestheIDT72V70210isdesigned
for the TDM time slot interchange function in either voice or data applications.
Some of the main features of the IDT72V70210 are low power 3.3 Volt
operation, automatic ST-BUS®/GCI sensing, memory block programming,
simple microprocessor interface, one cycle direct internal memory accesses,
JTAGTestAccessPort(TAP)andperstreamprogrammableinputoffsetdelay,
variable or constant throughput modes, internal loopback, output enable, and
Processor Mode.
Output
MUX
Receive
Serial Data
Streams
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
ODE
F0i
Vcc
CS
DS
R/
W A0-A11
GND
DTA
D0-D15
5714 drw01
RX8
RX9
RX10
RX11
RX12
RX13
RX14
RX15
Loopback
Test Port
Data Memory
Internal
Registers
Microprocessor Interface
Timing Unit
TX0
TX1
TX2
TX3
TX4
TX5
TX6
TX7
TX8
TX9
TX10
TX11
TX12
TX13
TX14
TX15
CLK
FE
IC
TDI
TMS
TCK
TDO
TRST
RESET
RX16
RX17
RX18
RX19
RX20
RX21
RX22
RX23
RX24
RX25
RX26
RX27
RX28
RX29
RX30
RX31
TX16
TX17
TX18
TX19
TX20
TX21
TX22
TX23
TX24
TX25
TX26
TX27
TX28
TX29
TX30
TX31
Connection
Memory
Transmit
Serial Data
Streams


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