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IDT72V70210 Datasheet(PDF) 6 Page - Integrated Device Technology

Part No. IDT72V70210
Description  3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT72V70210 Datasheet(HTML) 6 Page - Integrated Device Technology

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COMMERCIALTEMPERATURERANGE
IDT72V70210 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
disabled. For proper per-channel loopback operation, the contents of frame
delay offset registers must be set to zero.
DELAY THROUGH THE IDT72V70210
The switching of information from the input serial streams to the output
serial streams results in a throughput delay. The device can be pro-
grammed to perform time-slot interchange functions with different through-
put delay capabilities on a per-channel basis. For voice applications,
variable throughput delay is best as it ensure minimum delay between input
and output data. In wideband data applications, constant throughput delay
is best as the frame integrity of the information is maintained through the
switch.
The delay through the device varies according to the type of throughput
delay selected in the
V/C bit of the connection memory.
VARIABLE DELAY MODE (
V/C BIT = 0)
In this mode, the delay is dependent only on the combination of source
and destination channels and is independent of input and output streams.
The minimum delay achievable in the IDT72V70210 is three time-slots. If
the input channel data is switched to the same output channel (channel n,
frame p), it will be output in the following frame (channel n, frame p+1). The
same is true if the input channel n is switched to output channel n+1 or n+2.
If the input channel n is switched to output channel n+3, n+4,..., the new
output data will appear in the same frame. Table 2 shows the possible
delays for the IDT72V70210 in the variable delay mode.
CONSTANT DELAY MODE (
V/C BIT = 1)
In this mode, frame integrity is maintained in all switching configurations by
making use of a multiple data memory buffer. Input channel data is written into
the data memory buffers during frame n will be read out during frame n+2. In
the IDT72V70210, the minimum throughput delay achievable in the constant
delaymodewillbeoneframe.Forexample,wheninputtime-slot31isswitched
tooutputtime-slot0.Themaximumdelayof94time-slotsofdelayoccurswhen
time-slot 0 in a frame is switched to time-slot 31 in the frame.
MICROPROCESSOR INTERFACE
The IDT72V70210’s microprocessor interface looks like a standard RAM
interface to improve integration into a system. With a 12-bit address bus and
a16-bitdatabus,readandwritesaremappeddirectlyintoDataandConnection
memories and require only one cycle to access. By allowing the internal
memoriestoberandomlyaccessedinonecycle,thecontrollingmicroprocessor
has more time to manage other peripheral devices and can more easily and
quickly gather information and setup the switch paths.
Table 4 shows the mapping of the addresses into internal memory blocks
and Table 5 shows the Control Register information.
MEMORY MAPPING
The address bus on the microprocessor interface selects the internal
registers and memories of the IDT72V70210.
Thetwomostsignificantbitsoftheaddressselectbetweentheregisters,Data
Memory, and Connection Memory. If A11 and A10 are HIGH, A9-A0 are used
to address the Data Memory. If A11 is HIGH and A10 is LOW, A9-A0 are used
to address Connection Memory. If A11 is LOW and A10 is HIGH A9-A0 are
usedtoselecttheControlRegister,FrameAlignmentRegister,andFrameOffset
Registers. See Table 4 for mappings.
As explained in the Serial Data Interface Timing and Switching Configura-
tions sections, after system power-up, the Control Register should be pro-
grammed immediately to establish the desired switching configuration.
ThedataintheControlRegisterconsistsoftheMemoryBlockProgramming
bit (MBP), the Block Programming Data (BPE) bits, the Begin Block Program-
mingEnable(BPE),theOutputStandBy,StartFrameEvaluation,andDataRate
Select bits. As explained in the Memory Block Programming section, the BPE
begins the programming if the MBP bit is enabled. This allows the entire
connectionmemoryblocktobeprogrammedwiththeBlockProgrammingData
bits. If the ODE pin is low, the OSB bit enables (if high) or disables (if low) all
TX output drivers. If the ODE pin is high, the contents of the OSB bit is ignored
and all TX output drivers are enabled.
CONNECTION MEMORY CONTROL
If the ODE pin or the OSB bit is high, the OE bit of each connection memory
location controls the output drivers-enables (if high) or disables (if low). See
Table 3 for detail.
TheProcessorChannel(PC)bitoftheConnectionMemoryselectsbetween
ProcessorModeandConnectionMode. Ifhigh,thecontentsoftheConnection
Memory are output on the TX streams. If low, the Stream Address Bit (SAB)
and the Channel Address Bit (CAB) of the Connection Memory defines the
sourceinformation(streamandchannel)ofthetime-slotthatwillbeswitchedto
the output from Data Memory.
Also in the Connection Memory is the
V/C (Variable/Constant Delay) bit.
Each Connection Memory location allows the per-channel selection between
variable and constant throughput delay modes.
If the LPBK bit is high, the associated TX output channel data is internally
looped back to the RX input channel (i.e., RXn channel m data comes from the
TXn channel m). If the LPBK bit is low, the loopback feature is disabled. For
proper per-channel loopback operation, the contents of the frame delay offset
registers must be set to zero.
INITIALIZATION OF THE IDT72V70210
After power up, the state of the connection memory is unknown. As such,
theoutputsshouldbeputinhighimpedancebyholdingtheODElow. Whilethe
ODE is low, the microprocessor can initialize the device, program the active
paths, and disable unused outputs by programming the OE bit in connection
memory. Once the device is configured, the ODE pin (or OSB bit depending
on initialization) can be switched.


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