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MC74HC393A Datasheet(PDF) 4 Page - ON Semiconductor |
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MC74HC393A Datasheet(HTML) 4 Page - ON Semiconductor |
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MC74HC393A http://onsemi.com 4 Typical @ 25 °C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Counter)* 35 pF * Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D). TIMING REQUIREMENTS (Input tr = tf = 6 ns) Guaranteed Limit Symbol Parameter VCC V – 55 to 25 _C v 85_C v 125_C Unit trec Minimum Recovery Time, Reset Inactive to Clock (Figure 2) 2.0 3.0 4.5 6.0 25 15 10 9 30 20 13 11 40 30 15 13 ns tw Minimum Pulse Width, Clock (Figure 1) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 15 110 36 22 19 ns tw Minimum Pulse Width, Reset (Figure 2) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 15 110 36 22 19 ns tr, tf Maximum Input Rise and Fall Times (Figure 1) 2.0 3.0 4.5 6.0 1000 800 500 400 1000 800 500 400 1000 800 500 400 ns NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D). |
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