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MC74HC390A Datasheet(PDF) 4 Page - ON Semiconductor

Part No. MC74HC390A
Description  Dual 4-Stage Binary Ripple Counter with ÷2 and ÷5 Sections
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC74HC390A Datasheet(HTML) 4 Page - ON Semiconductor

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MC74HC390A
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TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
VCC
V
– 55 to
25
_C
v 85_C
v 125_C
Unit
trec
Minimum Recovery Time, Reset Inactive to Clock A or Clock B
(Figure 2)
2.0
3.0
4.5
6.0
25
15
10
9
30
20
13
11
40
30
15
13
ns
tw
Minimum Pulse Width, Clock A, Clock B
(Figure 1)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
15
110
36
22
19
ns
tw
Minimum Pulse Width, Reset
(Figure 2)
2.0
3.0
4.5
6.0
75
27
20
18
95
32
24
22
110
36
30
28
ns
tf, tf
Maximum Input Rise and Fall Times
(Figure 1)
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).
PIN DESCRIPTIONS
INPUTS
Clock A (Pins 1, 15) and Clock B (Pins 4, 15)
Clock A is the clock input to the
÷ 2 counter; Clock B is
the clock input to the
÷ 5 counter. The internal flip–flops are
toggled by high–to–low transitions of the clock input.
CONTROL INPUTS
Reset (Pins 2, 14)
Asynchronous reset. A high at the Reset input prevents
counting, resets the internal flip–flops, and forces QA
through QD low.
OUTPUTS
QA (Pins 3, 13)
Output of the
÷ 2 counter.
QB, QC, QD (Pins 5, 6, 7, 9, 10, 11)
Outputs of the
÷ 5 counter. QD is the most significant bit.
QA is the least significant bit when the counter is connected
for BCD output as in Figure 4. QB is the least significant bit
when the counter is operating in the bi–quinary mode as in
Figure 5.
SWITCHING WAVEFORMS
Q
tr
tf
tPLH
tPHL
tTLH
tTHL
VCC
GND
CLOCK
10%
50%
90%
1/fmax
tw
trec
RESET
Figure 1.
Figure 2.
VCC
GND
VCC
GND
10%
50%
90%
Q
CLOCK
50%
50%
50%
tPHL
tw
10%


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