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SY88813V Datasheet(PDF) 5 Page - Micrel Semiconductor |
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SY88813V Datasheet(HTML) 5 Page - Micrel Semiconductor |
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5 SY88813V Micrel, Inc. M9999-072505 hbwhelp@micrel.com or (408) 955-1690 DETAILED DESCRIPTION The SY88813V low power limiting post amplifier operates from a single +3.3V or +5V power supply, over temperatures from –40 °C to +85°C. Signals with data rates up to 155Mbps and as small as 5mV PP can be amplified. Figure 1 shows the allowed input voltage swing. The SY88813V generates a SD output. SD LVL sets the sensitivity of the input amplitude detection. Input Amplifier/Buffer Figure 2 shows a simplified schematic of the SY88813V's input stage. The high-sensitivity of the input amplifier allows signals as small as 5mV PP to be detected and amplified. The input amplifier allows input signals as large as 1800mV PP. Input signals are linearly amplified with a typically 38dB differential voltage gain. Since it is a limiting amplifier, the SY88813V outputs typically 1500mV PP voltage-limited waveforms for input signals that are greater than 18mV PP. Applications requiring the SY88813V to operate with high- gain should have the upstream TIA placed as close as possible to the SY88813V’s input pins to ensure the best performance of the device. Output Buffer The SY88813V’s PECL output buffer is designed to drive 50 Ω lines. The output buffer requires appropriate termination for proper operation. An external 50 Ω resistor to V CC–2V for each output pin provides this. Figure 3 shows a simplified schematic of the output stage and includes an appropriate termination method. Signal-Detect The SY88813V generates a chatter-free PECL SD similar to the SY88813V's output buffer. SD is used to determine that the input amplitude is large enough to be considered a valid input. SD asserts high if the input amplitude rises above the threshold set by SD LVL and deasserts low otherwise. /EN deasserts the true output signal without removing the input signals. Typically 4.6dB SD hysteresis is provided to prevent chattering. Signal-Detect Level Set A programmable signal-detect level set pin (SDLVL) sets the threshold of the input amplitude detection. Setting a voltage on SDLVL between VCC and VREF sets this threshold. If desired, a resistor divider between V CC and VREF, as shown in Figure 4, also creates this threshold. The smaller the voltage difference from SD LVL to VCC, the smaller the SD sensitivity. Hence, larger input amplitude is required to assert SD. “Typical Operating Characteristics” shows the relationship between the input amplitude detection sensitivity and the SDLVL voltage. Hysteresis The SY88813V provides typically 4.6dB SD electrical hysteresis. By definition, a power ratio measured in dB is 10log(power ratio). Power is calculated as V2 IN/R for an electrical signal. Hence the same ratio can be stated as 20log(voltage ratio). While in linear mode, the electrical voltage input changes linearly with the optical power and hence the ratios change linearly. Therefore, the optical hysteresis in dB is half the electrical hysteresis in dB given in the datasheet. The SY88813V provides typically 2.3dB SD optical hysteresis. As the SY88813V is an electrical device, this datasheet refers to hysteresis in electrical terms. With 6dB SD hysteresis, a voltage factor of two is required to assert or deassert SD. |
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