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AD5570BRS-REEL Datasheet(PDF) 5 Page - Analog Devices |
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AD5570BRS-REEL Datasheet(HTML) 5 Page - Analog Devices |
5 / 24 page AD5570 Rev. 0 | Page 5 of 24 STANDALONE TIMING CHARACTERISTICS VDD = +12 V ± 5%, VSS = −12 V ± 5% or VDD = +15 V ± 10%, VSS = −15 V ± 10%; VREF = 5 V; REFGND = GND = 0 V; RL = 5 kΩ; and CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter Limit at TMIN, TMAX Unit Description fMAX 10 MHz max SCLK frequency t1 100 ns min SCLK cycle time t2 35 ns min SCLK high time t3 35 ns min SCLK low time t4 10 ns min SYNC to SCLK falling edge setup time t5 35 ns min Data setup time t6 0 ns min Data hold time t7 45 ns min SCLK falling edge to SYNC rising edge t8 45 ns min Minimum SYNC high time t9 0 ns min SYNC rising edge to LDAC falling edge t10 50 ns min LDAC pulse width t11 0 ns min LDAC falling edge to SYNC falling edge (no update) t12 0 ns min LDAC rising edge to SYNC rising edge (no update) t13 20 ns min CLR pulse width All parameters guaranteed by design and characterization. Not production tested. All input signals are measured with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL +VIH)/2. DB15 DB0 SCLK SYNC SDIN LDAC1 CLR LDAC2 NOTES 1. ASYNCHRONOUS LDAC UPDATE MODE. UPDATE ON FALLING EDGE OF LDAC. 2. SYNCHRONOUS LDAC UPDATE MODE. UPDATE ON RISING EDGE OF SYNC. t3 t2 t5 t6 t7 t9 t1 t4 t8 t12 t11 t10 t13 Figure 2. Serial Interface Timing Diagram |
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