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MC74HC132A Datasheet(PDF) 3 Page - ON Semiconductor

Part No. MC74HC132A
Description  Quad 2-Input NAND Gate with Schmitt-Trigger Inputs
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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MC74HC132A Datasheet(HTML) 3 Page - ON Semiconductor

   
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MC74HC132A
http://onsemi.com
3
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25
_C
v 85_C
v 125_C
Unit
VOH
Minimum High–Level Output
Voltage
VinvVT– min or VT+ max
|Iout| v 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vinv–VT– min or VT+ max
|Iout| v 4.0 mA
|Iout| v 5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
VOL
Maximum Low–Level Output
Voltage
Vin ≥VT+ max
|Iout| v 20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin≥VT+ max
|Iout| v 4.0 mA
|Iout| v 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
Iin
Maximum Input Leakage
Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
6.0
1.0
10
40
µA
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol
Parameter
VCC
V
– 55 to
25
_C
v 85_C
v 125_C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Cin
Maximum Input Capacitance
10
10
10
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Gate)*
24
pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
Figure 1. Switching Waveforms
tr
VCC
GND
90%
50%
10%
90%
50%
10%
INPUT
A OR B
Y
tPHL
tPLH
tTHL
tTLH
*Includes all probe and jig capacitance
Figure 2. Test Circuit
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
tf


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