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ISL3874 Datasheet(PDF) 24 Page - Intersil Corporation

Part No. ISL3874
Description  Wireless LAN Integrated Medium Access Controller with Baseband Processor with Mini-PCI
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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ISL3874 Datasheet(HTML) 24 Page - Intersil Corporation

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24
DQPSK modulation as shown in the table. The symbols of
the MPDU shall be numbered starting with “0” for the first
symbol for the purposes of determining odd and even
symbols. That is, the MPDU starts on an even numbered
symbol. The last data dibits d2, and d3 CCK encode the
basic symbol as specified in Table 18. This table is derived
from the CCK formula above by setting
ϕ2= (d2*pi)+ pi/2, ϕ3
= 0, and
ϕ4 = d3*pi. In the table d2 and d3 are in the order
shown and the complex chips are shown LSB to MSB (left to
right) with LSB transmitted first.
At 11Mbps, 8 bits (d0 to d7; d0 first in time) are transmitted
per symbol.
The first dibit (d0, d1) encodes the phase
ϕ1 based on
DQPSK. The DQPSK encoder is specified in Table 17. The
phase change for
ϕ1 is relative to the phase ϕ1 of the
preceding symbol. In the case of rate change, the phase
change for
ϕ1 is relative to the phase ϕ1 of the preceding
CCK symbol. All odd numbered symbols of the MPDU are
given an extra 180 degree (
π) rotation in accordance with the
DQPSK modulation as shown in Table 17. Symbol
numbering starts with “0” for the first symbol of the MPDU.
The data dibits: (d2, d3), (d4, d5), (d6, d7) encode
ϕ2, ϕ3,
and
ϕ4 respectively based on QPSK as specified in Table
19. Note that this table is binary, not Grey, coded.
TX Power Control
The transmitter power can be controlled via two registers.
The first register, CR58, contains the digitized results of
power measurements by the ISL3874. By comparing this
measurement to what is needed for transmit power, The
MAC determines whether to raise or lower the transmit
power. It does this by writing the power level desired to
register CR31.
Clear Channel Assessment (CCA) and
Energy Detect (ED) Description
The Clear Channel Assessment (CCA) circuit implements the
carrier sense portion of a Carrier Sense Multiple Access
(CSMA) networking scheme. The Clear Channel Assessment
(CCA) monitors the environment to determine when it is clear to
transmit. The CCA circuit in the ISL3874 can be programmed to
be a function of RSSI (energy detected on the channel), CS1,
SQ1, or various combinations. The CCA is used by the Media
Access Controller (MAC) in the ISL3874. The MAC decides on
transmission based on traffic to send and the CCA indication.
The CCA indication can be ignored, allowing transmissions
independent of any channel conditions. The CCA in
combination with the visibility of the various internal parameters
(i.e., Energy Detection measurement results), can assist the
MAC in executing algorithms that can adapt to the
environment. These algorithms can increase network
throughput by minimizing collisions and reducing transmissions
liable to errors.
There are three measures that can be used in the CCA
assessment. The receive signal strength indication (RSSI)
which indicates the energy at the antenna, CS1 and carrier
sense (SQ1). CS1 becomes active anytime the AGC portion of
the circuit becomes unlocked, which is likely at the onset of a
signal that is strong enough to support 11Mbps, but may not
occur with the onset of a signal that is only strong enough to
support 1 or 2MBps. CS1 stays active until the AGC locks and
a SQ1 assessment is done, if SQ1 is false, then CS1 is cleared,
which deasserts CCA. If SQ1 is true, then tracking is begun,
and CCA continues to show the channel busy. CS1 may occur
at any time during acquisition as the AGC state machine runs
asynchronously with respect to slot times.
SQ1 becomes active only when a spread signal with the
proper PN code has been detected, and the peak correlation
amplitude to sidelobe ratio exceeds a set threshold, so it
may not be adequate in itself.
A SQ1 evaluation occurs whenever the AGC has remained
locked for the entire data ingest period. When this happens,
SQ1 is updated between 8
µs and 9µs into the 10µs dwell. If
CS1 is not active, two consecutive SQ1s are required to
advance the part to tracking.
The state of CCA is not guaranteed from the time RX_PE
goes high until the first CCA assessment is made. At the end
of a packet, after RXPE has been deasserted, the state of
CCA is also not guaranteed.
The Receive Signal Strength Indication (RSSI) measurement is
derived from the state of the AGC circuit. ED is the comparison
TABLE 17. DQPSK ENCODING TABLE
DIBIT PATTERN (d(0), d(1))
d(0) IS FIRST IN TIME
EVEN SYMBOLS
PHASE CHANGE
(+j
ω)
ODD SYMBOLS
PHASE CHANGE
(+j
ω)
00
0
π
01
π/2
3
π/2 (-π/2)
11
π
0
10
3
π/2 (-π/2)
π/2
TABLE 18. 5.5Mbps CCK ENCODING TABLE
d2, d3
CHIPS
00
1j
1
1j
-1
1j
1
-1j
1
01
-1j
-1
-1j
1
1j
1
-1j
1
10
-1j
1
-1j
-1
-1j
1
1j
1
11
1j
-1
1j
1
-1j
1
1j
1
TABLE 19. QPSK ENCODING TABLE
DIBIT PATTERN (d(i), d(i+1))
d(i) IS FIRST IN TIME
PHASE
00
0
01
π/2
10
p
11
3
π/2 (-π/2)
ISL3874


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