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ISL3874 Datasheet(PDF) 18 Page - Intersil Corporation

Part No. ISL3874
Description  Wireless LAN Integrated Medium Access Controller with Baseband Processor with Mini-PCI
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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ISL3874 Datasheet(HTML) 18 Page - Intersil Corporation

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18
PE1 and PE2 encoding details are found in Table 11.
Note that during normal receive and transmit operation that
PE1 is static and PE2 toggles for receive and transmit
states.
Master Clock
Prescaler
The ISL3874 contains a clock prescaler to provide flexibility
in the choice of clock input frequencies. For 11Mb/s
operation, the internal master clock, MCLK, must be
between 11MHz and 16MHz. The clock generator itself
requires an input from the prescaler that is at least twice the
desired MCLK frequency. Thus the lowest oscillator
frequency that can be used for an 11MHz MCLK is 22MHz.
The prescaler can divide by integers and 1/2 steps (i.e., 1,
1.5, 2, 2.5). Another way to look at it is that the divisor ratio
between the external clock source and the internal MCLK
may be integers between 2 and 14.
Typically, the 44MHz baseband clock is used as the input, and
the prescaler is set to divide by 2. Contact the factory for further
details on setting the clock prescaler register in the ISL3874.
Low-Frequency Crystal
The ISL3874 controller can accept the same clock signal as
the PHY baseband processor (typically 44MHz), thereby
avoiding the need for a separate, MAC-specific oscillator. The
low-frequency oscillator is intended for use with a 32.768kHz,
tuning-fork type watch crystal to permit accurate timekeeping
with very low power consumption during sleep state.
If a 32.768kHz crystal is connected, the resulting LF clock is
supplied to an interval timer to permit measuring sleep
intervals as well as providing a programmable wake-up time.
In addition, the clock generator can operate either from
BBP_CLK or (very slowly) from the LF clock. Glitch-free
switching between these two clock sources, under firmware
control, is provided by two, non-architectural Strobe functions
(“FAST” and “SLOW”). In addition, during hardware reset, the
clock generator source is set to the LF clock if no edges are
detected on CLKIN for two cycles of the LF clock (roughly 61
microseconds). This allows proper initialization with omission
of either clock source, since without the LF crystal attached
there will not be cycles of the LF clock to activate the detection
circuit. The ability to initialize the ISL3874 using the LF
oscillator to generate MCLK allows the high-frequency (PHY)
oscillator to be powered down during sleep state. If this is
done, firmware can turn on power to the PHY oscillator upon
wake-up, and use the interval timer to measure the start-up
and stabilization period before switching to use CLKIN.
Clock Generator
The ISL3874 operates with BBP_CLK frequency of 44MHz.
The MCLK prescaler generates MCLK (and QCLK) from the
external clock provided at the BBP_CLK input, or from the
output of the LF oscillator. The MCLK prescaler divides the
selected input clock by any integer value between 2 and 16,
inclusive.
The MCLK prescaler is set to divide by 16 at hardware reset
to allow initialization firmware to be executed from slow
memory devices at any BBP_CLK frequency. The MCLK
prescaler generates glitch free output when the divisor is
changed. This allows firmware to change the MCLK
frequency during operation, which is especially useful to
selectively reduce operating speed, thereby conserving
power, when full speed processing is not required.
Power On Reset Configuration
Power On Reset is issued to the ISL3874 with the GRESET
pin or via the soft reset bit, SRESET, in the Configuration
Option Register (COR, bit 7).
The MD[15:8] pin values are sampled during GRESET.
These pins have internal 50K pull-up and pull-down
resistors. External resistors (typically 10k
Ω) are necessary to
change the internal default setting.
MD[11], IDLE, has no equivalent functionality in any control
register. When asserted at reset, it will inhibit firmware
execution. This is used to allow the initial download of
firmware in “Genesis Mode”. See the Hardware Reference
Manual for more details. The latch is cleared when the
Software Reset, SRESET, COR(7) is active.
HRESET is connected to the PCI reset and will only reset
the PCI core. GRESET can be driven by HRESET if MD13 is
pulled high.
TABLE 11. POWER ENABLE STATES
PE1
PE2
PLL_PE
Power Down State
0
0
1
Receive State
1
1
1
Transmit State
1
0
1
PLL Active State
0
1
1
PLL Disable State
X
X
0
NOTE: PLL_PE is controlled via the serial interface, and can be
used to disable the internal synthesizer, the actual synthesizer
control is an AND function of PLL_PE, and a result of the OR function
of PE1 and PE2. PE1 and PE2 will directly control the power enable
functionality of the LO buffer(s)/phase shifter.
XTALIN
XTALOUT
X1
C1
C2
FIGURE 10. 32.768kHz CRYSTAL
10M
22pF
4700pF
ISL3874


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