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ISL3874 Datasheet(PDF) 17 Page - Intersil Corporation

Part No. ISL3874
Description  Wireless LAN Integrated Medium Access Controller with Baseband Processor with Mini-PCI
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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ISL3874 Datasheet(HTML) 17 Page - Intersil Corporation

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17
facilitates Power Management queuing, and allows dynamic
fragmentation and defragmentation by controller. Simple
Allocate/Deallocate commands insure low host CPU
overhead for memory management.
Hardware buffer chaining provides high performance while
reading and writing buffers. Data is transferred between the
host driver and the ISL3874 by writing or reading a single
register location (The Buffer Access Path, or BAP). Each
access increments the address in the buffer memory.
Internally, the firmware allocates blocks of memory as needed
to provide the requested buffer size. These blocks may not be
contiguous, but the firmware builds a linked list of pointers
between them. When the host driver is transferring data
through a buffer access path and reaches the end of a
physical memory block, hardware in the host interface follows
the linked list so that the buffer access path points to the
beginning of the next memory block. This process is
completely transparent to the host driver, which simply writes
or reads all buffer data to the same register. If the host driver
attempts to access beyond the end of the allocated buffer,
subsequent writes are ignored, and reads will be undefined.
Power Sequencing
The ISL3874 provides a number of firmware controlled port
pins that are used for controlling the power sequencing and
other functions in the front end components of the radio.
Packet transmission requires precise control of the radio.
Ideally, energy at the antenna ceases after the last symbol of
information has been transmitted. Additionally, the
transmit/receive switch must be controlled properly to protect
the receiver. It is also important to apply appropriate
modulation to the PA while it's active.
Signaling sequences for the beginning and end of normal
transmissions are illustrated in Figure 9. Table 10 lists
applicable delays associated with these control signals.
A transmission begins with PE2 as shown in Figure 9. Next,
the transmit/receive switch is configured for transmission via
the differential pair TR_SW and TR_SW_BAR. This is
followed by a transmit enable (TX_ENABLE) to the
Baseband processor inside the ISL3874. This enable
activates the transmit state machine in the BBP. Lastly,
PA_PE activates the PA. Delays for these signals related to
the initiation of transmission are referenced to PE2.
Immediately after the final data bit has been clocked out of the
MAC the Baseband processor is disabled. The MAC in then
waits for a control signal (TX_READY) from the Baseband
processor to go inactive, signaling that the BBP has modulated
the final information-rich symbol. It then immediately de-asserts
PA_PE followed by placing the transmit/receive switch in the
receive position and ending with PE2 going high. Delays for
these signals related to the termination of transmission are
referenced to the rising edge of PE2.
TABLE 10. TRANSMIT CONTROL TIMING SPECIFICATIONS
PARAMETER
SYMBOL
DELAY
TOLERANCE UNITS
TX_PE to PE2
tD1
.1
±0.1
µs
TX_PE to PA_PE
tD2
1
±0.1
µs
TX_PE to TR_SW
tD3
3
±0.1
µs
TR_SW to TX_PE
tD4
3
±0.1
µs
PA_PE to TR_SW
tD5
1
±0.1
µs
PE2 to TX_PE
tD6
.1
±0.1
µs
FIGURE 9. TRANSMIT CONTROL SIGNAL SEQUENCING
PE1
PE2
TR_SW
TR_SW_BAR
TX_PE
PA_PE
tD1
tD6
tD5
tD2
tD3
tD4
ISL3874


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