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ISL3874 Datasheet(PDF) 15 Page - Intersil Corporation

Part No. ISL3874
Description  Wireless LAN Integrated Medium Access Controller with Baseband Processor with Mini-PCI
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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ISL3874 Datasheet(HTML) 15 Page - Intersil Corporation

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15
These are the minimum set of registers required for the card
to respond to a target operation.
The Memory Base Address register is used to set the starting
address range this device will respond to. The maximum
address space for this chip is 4K. The Command register
enables specific features of the PCI host interface. The
Memory Access Enable bit must be set to allow any read/write
operations. Further information about the PCI configuration
registers can be found in the PCI 2.1 Interface spec.
Target Mode Operation
This mode is the default or base mode of communicating with
the ISL3874 processor. After the host configures the PCI
interface itself, PCI memory read and write transactions are
used to initialize the processor and to send it commands.
These transactions access host side register addresses in
much the same way as the HFA3842 did. Host registers have
had their address DWORD aligned (shifted left by one) from the
register map used by the HFA3842. This allows ordinary
double word accesses to take place on any given host register.
Host register addresses are 8 bits wide and wrap at 0xFF in
memory space up to the maximum address space. Each
register provides up to 16 bits of valid data depending on the
PCI read or write system call request length. PCI requests for
greater than word length (16 bits) will have the upper bits
zeroed.
PCI Specific Implementation
The ISL3874 host side memory space is not intended to be
written in a sequential manner so burst operations are not
supported.
Only memory read, memory write, and configuration cycles
are supported in target mode. Fast block transfers with the
least amount of host overhead can be implemented in
Master mode, however, throughput will be limited by
available Mbus bandwidth. BAP transfers are supported in
Target mode and should be faster than equivalent PCMCIA
BAP transactions. This allows a port of the existing driver
from the PCMCIA part to PCI with minimal changes.
The ISL3874 is a single function device so only one interrupt,
HINTA, is used. An interrupt is generated whenever one of the
interrupt sources in the ISR goes active and the corresponding
bit in the IMR is enabled. The interrupt pin, HINTA, generates
an active low level when requesting an interrupt.
Reset
There are two reset pins for this part. The first, GRESET is a
hardware reset pin used to reset the entire part on power up.
The second reset is the HRESET. This is intended to reset
only the PCI interface section.
A soft reset is available which does not reset any of the PCI
core read-only configuration registers. This soft reset is
accomplished in the same manner as the HFA3842 by
writing a one to COR[7]. Note this register has been moved
from its previous location. It now resides at location 0x4C.
Only bit 7 (Soft Reset) is implemented for this register. The
HCR and COR registers are the only registers that can be
written during soft reset. The HCR can be written to override
the default MBus strapping options and COR[7] is reset to
bring the part out of soft reset.
LOCK# is not implemented. We do not have atomic
accesses and thus have no need to support this. Further, it
is not implemented in the mini-PCI spec.
Normal Operating Modes
Target mode has three different types of accesses. The
biggest difference between them as far as the host is
concerned is the amount of time it takes to complete the
accesses. The three types are hardware registers, memory
mapped registers and BAP data registers.
Hardware registers complete their access in one M clock
cycle, which at normal M clock speeds means the PCI read
will complete without a retry.
Memory mapped read cycles will almost always require at
least one retry depending on M clock speed and how soon
the ISL3874 memory controller grants the memory request.
BAP read cycles can fall into either case depending on
whether or not a preread completes prior to the host
requesting another transfer.
The PCI interface supports one level of posted writes. That
is, the first write cycle will be accepted and the PCI interface
will complete the transaction immediately. If another write
occurs before the first write has completed internally, it will
not be accepted and the PCI bus will have to retry the write
at a later time.
PC Card Physical Interface
The Host interface is compatible to the Mini-PCI
Specification. Further details on programming and
controlling the PCI interface can be found in the
programmers manual for the ISL3874. The following
describes specific features of various pins:
HAD(0-31) - PCI Card Address and Data Input, Bits 0 to 31.
These signals make up the multiplexed PCI address and data
bus on the primary interface. During the address phase of a
primary bus PCI cycle, HAD31-HAD0 contain a 32-bit address
or other destination information. During the data phase,
HAD31-HAD0 contain data.
HBE2 - PCI bus commands and byte enables. HBE2 applies
to byte 2 (HAD23-HAD16).
HBE1 - PCI bus commands and byte enables. HBE1 applies
to byte 1 (HAD15-HAD8).
HBE0 - PCI bus commands and byte enables. HBE0 applies
to byte 0 (HAD7-HAD0).
HIDSEL - Initialization device select. HIDSEL selects the
ISL3874 during configuration space accesses. HIDSEL can
ISL3874


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