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ISL3874 Datasheet(PDF) 10 Page - Intersil Corporation

Part No. ISL3874
Description  Wireless LAN Integrated Medium Access Controller with Baseband Processor with Mini-PCI
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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ISL3874 Datasheet(HTML) 10 Page - Intersil Corporation

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10
SYNTHESIZER
SYNTHCLK(PK1) Period
tCYC
90
-
4,000
ns
SYNTHCLK(PK1) Width Hi
tH1
tCYC/2 - 10
-
tCYC/2 + 10
ns
SYNTHCLK(PK1) Width Lo
tL1
tCYC/2 - 10
-
tCYC/2 + 10
ns
SYNTHDATA(PK2) Hold Time from Falling Edge of SYNTHCLK(PK1)
tD2
0
-
-
ns
SYNTHCLK(PK1) Falling Edge to SYNLE Inactive
tD3
35
-
-
ns
SYSTEM INTERFACE - PCI TIMING
Cycle Time, HPCLK
tCYC
30
-
-
ns
Pulse Duration, HPCLK High
tH
11
-
-
ns
Pulse Duration, HPCLK Low
tL
11
-
-
ns
Slew Rate, HPCLK
tS
1
-
4
V/ns
Propagation Delay Time, HPCLK to Signal Valid Delay Time
tV
-
-
11
ns
Propogation Delay Time, HPCLK to Signal Invalid Delay Time
tINV
2
-
-
ns
Enable Time, High Impedance to Active Delay Time from HPCLK
tEN
2
-
-
ns
Disable Time, Active to High Impedance Delay Time from HPCLK
tDIS
-
-
28
ns
Setup Time Before HPCLK Valid
tS
7
-
-
ns
Hold Time After HPCLK High
tH
0
-
-
ns
BASEBAND SIGNALS
Full Scale Input Voltage (VP-P)
0.25
0.50
1.0
V
Input Bandwidth (-0.5dB)
-
20
-
MHz
Input Capacitance
-
5
-
pF
Input Impedance (DC)
5
-
-
k
FS (Sampling Frequency)
-
-
22
MHz
AC Electrical Specifications (Continued)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Waveforms
FIGURE 1. MAC EXTERNAL MEMORY READ TIMING
ADDRESS
MA(17..1)
tH1
tE1
tS2
tH2
RAMCS
MOE
MD(15..0)
tS1
tD1
ISL3874


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