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ISL3874 Datasheet(PDF) 6 Page - Intersil Corporation

Part No. ISL3874
Description  Wireless LAN Integrated Medium Access Controller with Baseband Processor with Mini-PCI
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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ISL3874 Datasheet(HTML) 6 Page - Intersil Corporation

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6
MLBE
L3
CMOS BiDir Output, 2mA, 50K Pull Up
MBUS Lower Byte Enable. Asserted when accessing the low-order
byte of x16 memory devices that use the JEDEC 5-wire control
interface.
MOE
L1
CMOS TS Output, 2mA, 50K Pull Up
Memory Output Enable; asserted on memory reads
MWE/ MWEL
L2
CMOS TS Output, 2mA, 50K Pull Up
Low (or only) Byte Memory Write Enable. Asserted on writes to x8
memory devices, x16 memory devices that use the JEDEC 5-wire
control inteface, or writes to the low-order byte of x16 memory
devices that use the JEDEC 4-wire control interface.
RAMCS
K2
CMOS TS Output, 2mA, 50K Pull Up
RAM Select; asserted on MBUS cycles when the address is in the
area configured as RAM
NVCS
K1
CMOS TS Output, 2mA, 50K Pull Up
NV Memory Select; asserted on MBUS cycles when the address is in
the area configured as non-volitile memory.
TABLE 2. MEMORY INTERFACE PINS (Continued)
PIN NAME
PIN NUMBER
PIN I/O TYPE
DESCRIPTION
TABLE 3. GENERAL PURPOSE PORT PINS
PIN NAME
PIN NUMBER
PIN I/O TYPE
DESCRIPTION OF FUNCTION
(IF OTHER THAN IO PORT)
PJ4
T2
CMOS BiDir, 2mA, 50K Pull Down
PE1. PE1 and PE2 are bit-encoded functions that
control the RF and IF sections.
PJ5
T4
CMOS BiDir, 2mA, 50K Pull Down
LE_IF. LE_IF and LE_RF are the corresponding serial
enables for the IF and RF chips. The trailing edge of the
latch enables (LE) are required to latch the data in the
input register. The last 20 bits of data before the trailing
edge of enables are latched in.
PJ6
P4
CMOS BiDir, 2mA
LED1.
PJ7
T3
CMOS BiDir, 2mA, 50K Pull Down
RADIO_PE. This signal is the power enable to the RF
and IF components, but not the baseband.
PK0
R5
CMOS BiDir, 2mA, ST, 50K Pull Down
LE_RF. LE_RF and LE_IF are the corresponding serial
enables for the RF and IF chips. The trailing edge of the
latch enables (LE) are required to latch the data in the
input register. The last 20 bits of data before the trailing
edge of enable are latched in.
PK1
R4
CMOS BiDir, 2mA, 50K Pull Down
SYNTHCLK. Separate signals, SYNTHCLK and
SYNTHDATA, are used to program the synthesizer
through bit manipulation in firmware.
PK2
N7
CMOS BiDir, 2mA, 50K Pull Down
SYNTHDATA. Separate signals, SYNTHDATA and
SYNTHCLK, are used to program the synthesizer
through bit manipulation in firmware.
PK3
R6
CMOS BiDir, 2mA, 50K Pull Down
PA_PE. This signal, when asserted high, enables the
Tx section of the Modulator/Demodulator and RF/IF
up/down converter circuits.
PK4
T5
CMOS BiDir, 2mA, 50K Pull Down
PE2. PE2 and PE1 are bit-encoded functions that
control the RF and IF sictions.
PK7
P7
CMOS BiDir, 2mA, 50K Pull Down
CAL_EN. Calibrates the Rx function to eliminate DC
offset in the Rx chain.
PL3
P8
CMOS BiDir, 2mA, 50K Pull Up
TR_SW_BAR. Antenna Diversity Control
PL7
T6
CMOS BiDir, 2mA, 50K Pull Down
TR_SW. Antenna Diversity Control
ISL3874


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