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ISL3874 Datasheet(PDF) 28 Page - Intersil Corporation

Part No. ISL3874
Description  Wireless LAN Integrated Medium Access Controller with Baseband Processor with Mini-PCI
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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ISL3874 Datasheet(HTML) 28 Page - Intersil Corporation

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28
to 2 bits. In the CCK mode, when a symbol decision error is
made, up to 6 bits may be in error although on average only 3
bits will be in error. Secondly, when the bits are processed by
the descrambler, these errors are further extended. The
descrambler is a 7-bit shift register with two taps exclusive or’ed
with the bit stream. Thus, each error is extended by a factor of
three. Multiple errors can be spaced the same as the tap
spacing, so they can be canceled in the descrambler. In this
case, two wrongs do make a right. Given all that, if a single
error is made the whole packet is discarded anyway, so the
error extension property has no effect on the packet error rate.
It should be taken into account if a forward error correction
scheme is contemplated.
Descrambling is self synchronizing and is done by a
polynomial division using a prescribed polynomial. A shift
register holds the last quotient and the output is the exclusive-
or of the data and the sum of taps in the shift register.
PREAMBLE/HEADER
CRC-16
TX_AGC_IN
VREF
IREF
ANTSEL
TX_DATA
SCRAMBLER
TXD
MODULATOR,
TXI
TXQ
BARKER/CCK
TIMING
GENERATOR
VDD (ANALOG)
VDD (DIGITAL)
GND (ANALOG)
GND (DIGITAL)
TXCLK
TX_RDY
TX_PE
ANTSEL
BBP_CLK
MCLK
FIGURE 16. DSSS BASEBAND PROCESSOR, TRANSMIT SECTION
TX AGC
CONTROL
TRANSMIT
FILTER
DAC
DAC
TX
STATE
CONTROL
TX_IF_AGC
GENERATOR
6-BIT
DAC
REGISTER
6-BIT
ADC
MAC
CONTROL
SIGNALS
T0 + 1 SYMBOL CORRELATOR
CORRELATION
T0 + 2 SYMBOLS
T0
SAMPLES
EARLY
ON-TIME
LATE
CORRELATION TIME
FIGURE 17. CORRELATION PROCESS
PEAK
AT 2X CHIP
RATE
CORRELATOR OUTPUT IS THE RESULT OF CORRELATING
THE PN SEQUENCE WITH THE RECEIVED SIGNAL
OUTPUT REPEATS
ISL3874


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