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ISL3874 Datasheet(PDF) 26 Page - Intersil Corporation

Part No. ISL3874
Description  Wireless LAN Integrated Medium Access Controller with Baseband Processor with Mini-PCI
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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ISL3874 Datasheet(HTML) 26 Page - Intersil Corporation

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26
ifCompDet is a signal generated in the ISL3874 from the
HFA3783 chip. A '1' indicates its inputs are near saturation
and it needs the RF chip to switch from high gain to low gain.
RX_IF_Det is the input to the ISL3874 chip from the
HFA3783 which is transferred to ifCompDet on the
HFA3874.
RX_RF_AGC is the output of the ISL3874 chip and ‘1’ is
high gain, ‘0’ is low gain.
Demodulator Description
The receiver portion of the baseband processor, performs A/D
conversion and demodulation of the spread spectrum signal.
It correlates the PN spread symbols, then demodulates the
DBPSK, DQPSK, or CCK symbols. The demodulator
includes a frequency tracking loop that tracks and removes
the carrier frequency offset. In addition, it tracks the symbol
timing, and differentially decodes and descrambles the data.
The data is output through the RX Port to the external
processor.
The PRISM baseband processor in the ISL3874 uses
differentially coherent demodulation. The ISL3874 is
designed to achieve rapid settling of the carrier tracking loop
during acquisition. Rapid phase fluctuations are handled
with a relatively wide loop bandwidth which is then stepped
down as the packet progresses. Coherent processing
improves the BER performance margin as opposed to
differentially coherent processing for the CCK data rates.
The baseband processor uses time invariant correlation to
strip the Barker code spreading and phase processing to
demodulate the resulting signals in the header and
DBPSK/DQPSK demodulation modes. These operations are
illustrated in Figure 18 which is an overall block diagram of
the receiver processor.
In processing the DBPSK header, input samples from the I and
Q A/D converters are correlated to remove the spreading
sequence. The peak position of the correlation pulse is used to
determine the symbol timing. The sample stream is decimated
to the symbol rate and corrected for frequency offset prior to
PSK demodulation. Phase errors from the demodulator are fed
to the NCO through a lead/lag filter to maintain phase lock. The
carrier is de-rotated by the carrier tracking loop. The
demodulated data is differentially decoded and descrambled
before being sent to the header detection section.
In the 1Mbps DBPSK mode, data demodulation is performed
the same as in header processing. In the 2Mbps DQPSK
mode, the demodulator demodulates two bits per symbol
and differentially decodes these bit pairs. The bits are then
serialized and descrambled prior to being sent to the output.
In the CCK modes, the receiver removes carrier frequency
offsets and uses a bank of correlators to detect the
modulation. A biggest picker finds the largest correlation in
the I and Q Channels and determines the sign of those
correlations. For this to happen, the demodulator must know
the starting phase which is determined by referencing the
data to the last bit of the header. Each symbol demodulated
determines 1 or 2 nibbles of data. This is then serialized and
descrambled before being passed to the output.
Carrier tracking is via a lead/lag filter using a digital Costas
phase detector. Chip tracking in the CCK modes is chip
decision directed or slaved to the carrier tracking depending
on whether or not the locked oscillator design is utilized in
the radio.
Acquisition Description
A projected worst case time line for the acquisition of a
signal with a short preamble and header is shown. The
synchronization part of the preamble is 56 symbols long
followed by a 16-bit SFD. The receiver must monitor the
antenna to determine if a signal is present. The timeline is
broken into 10
µs blocks (dwells) for the scanning process.
This length of time is necessary to allow enough integration
of the signal to make a good acquisition decision. This worst
case time line example assumes that the signal arrives part
way into the first dwell such as to just barely catch detection.
The signal and the scanning process are asynchronous and
the signal could start anywhere. In this timeline, it is
assumed that the signal is present in the first 10
µs dwell, but
was missed due to power amplifier ramp up.
Meanwhile signal quality and signal frequency
measurements are made simultaneous with symbol timing
measurements. A CS1 followed by SQ1 active, or two
2
20 SYMBOLS
56 SYMBOL SYNC
SFD
TX
POWER
RAMP
20 SYMBOLS
7 SYM
16 SYMBOLS
AGC SETTLE AND LOCK
VERIFY AND CIR/FREQUENCY
SFD DET
SEED
FIGURE 15. ACQUISITION TIMELINE, NON DIVERSITY
AND INITIAL DETECTION
ESTIMATION AND CMF/NCO
JAMMING
DESCRAMBLER
START SFD SEARCH
START DATA
ISL3874


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