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ISL3873A Datasheet(PDF) 23 Page - Intersil Corporation

Part No. ISL3873A
Description  Wireless LAN Integrated Medium Access Controller with Baseband Processor
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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ISL3873A Datasheet(HTML) 23 Page - Intersil Corporation

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23
measurement results), can assist the MAC in executing
algorithms that can adapt to the environment. These
algorithms can increase network throughput by minimizing
collisions and reducing transmissions liable to errors.
There are three measures that can be used in the CCA
assessment. The Receive Signal Strength Indication (RSSI)
which indicates the energy at the antenna, CS1 and carrier
sense (SQ1). CS1 becomes active anytime the AGC portion
of the circuit becomes unlocked, which is likely at the onset of
a signal that is strong enough to support 11Mbps, but may not
occur with the onset of a signal that is only strong enough to
support 1 or 2MBps. CS1 stays active until the AGC locks and
a SQ1 assessment is done, if SQ1 is false, then CS1 is
cleared, which deasserts CCA. If SQ1 is true, then tracking is
begun, and CCA continues to show the channel busy. CS1
may occur at any time during acquisition as the AGC state
machine runs asynchronously with respect to slot times.
SQ1 becomes active only when a spread signal with the
proper PN code has been detected, and the peak correlation
amplitude to sidelobe ratio exceeds a set threshold, so it
may not be adequate in itself.
A SQ1 evaluation occurs whenever the AGC has remained
locked for the entire data ingest period. When this happens,
SQ1 is updated between 8 and 9
µs into the 10µsdwell. If
CS1 is not active, two consecutive SQ1’s are required to
advance the part to tracking.
The state of CCA is not guaranteed from the time RX_PE
goes high until the first CCA assessment is made. At the end
of a packet, after RXPE has been deasserted, the state of
CCA is also not guaranteed.
The Receive Signal Strength Indication (RSSI) measurement is
derived from the state of the AGC circuit. ED is the comparison
result of RSSI against a threshold. The threshold may be set to
an absolute power value, or it may be set to be N dB above the
measured noise floor. See CR 35. The ISL3873A measures
and stores the RSSI level when it detects no presence of BPSK
or QPSK signals. The average value of a 256 value buffer is
taken to be the noise floor. Thus, the value of the noise floor will
adapt to the environment. A separate noise floor value is
maintained for each antenna. An initial value of the noise floor
is established within 50
µs of the chip being active and is refined
as time goes on. Deasserting RX_PE does not corrupt the
learned values. If the absolute power metric is chosen, this
threshold is normally set to between -70 and -80dBm.
If desired, ED may beusedinthe acquisitionprocess as well
as CCA. ED may be used to mask (squelch) weak signals
and prevent radio reception of signals too weak to support
the high data rates, signals from adjacent cells, networks, or
buildings. See CR 47 (bit 6).
The Configuration registers effecting the CCA algorithm
operation are summarized below (more programming details
on these registers can be found under the Control Registers
section of this document).
The CCA output from pin 60 of the device can be defined as
active high or active low through CR 1 (bit 2).
CR9(6:5) allows CCA to be programmed to be a function of ED
only, the logical operation of (CS1 OR SQ1), the logical function
of (EDAND (CS1 OR SQ1)), or (EDOR(CS1ORSQ1)).
CR9(7) lets the user select from sampled CCA mode, which
means CCA will not glitch, is updated once per symbol and is
valid for reading at 15.8
µs or 18.7µs. In non-sampled mode,
CCA may change at any time, potentially several times per slot,
as ED and CS1 operate asynchronously to slot times.
In a typical system CCA will be monitored to determine when
the channel is clear. Once the channel is detected busy,
CCA should be checked periodically to determine if the
channel becomes clear. Once MD_RDY goes active, CCA
should be ignored for the remainder of the message. Failure
to monitor CCA until MD_RDY goes active (or use of a time-
out circuit) could result in a stalled system as it is possible for
the channel to be busy and then become clear without an
MD_RDY occurring.
AGC Description
The AGC system consists of the 3 chips handling the receive
signal, the RF to IF downconverter HFA3683, the IF to
baseband converter HFA3783, and the baseband processor
(BBP) section of the ISL3873A. The AGC loop (Figure 12) is
digitally controlled by the BBP. Basically it operates as follows:
Initially, the receiver is set for high gain. The percent of time
that the A/D converters in the baseband processor are
saturated is monitored along with signal amplitude and the
gain is adjusted down until the amplitude is what will
optimize the demodulator’s performance. If the amount of
saturation is great, the initial gain adjust steps are large. If
the signal overload is small, they are less. When the gain is
about right and the A/Ds’ outputs are within the lock window
(CR19), the BBP declares AGC lock and stops adjusting for
the duration of the packet. If the signal level then varies more
than a preset amount (CR20, CR29), the AGC is declared
unlocked and the gain again allowed to readjust.
The BBP looks for the locked state following an unlocked
state (CS1) as one indication that a received signal is on the
antenna. This starts the receive process of looking for PN
correlation (SQ1). Once PN correlation and AGC lock are
found, the processor begins acquisition.
For large signals, the power level in the RF stage output is
also monitored and if it is large, the LNA stage is shut down.
This removes 30dB of gain from the receive chain which is
compensated for by replacing 30dB of gain in the IF AGC
stage. There is some hysteresis in this operation and once
the AGC locks, it is locked as well. This improves the
receiver dynamic range.
ISL3873A


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